S-type Instruction

I don’t understand why S-type Instruction has two offset.

Can you give me an example to interpret the function of two offset?

The two offsets are combined to make one offset[11:0]. The are just broken up to make it easier for hardware to decode.

It doesn’t make it easier for the hardware to decode the offset. It makes it a little bit harder.

It does make a lot easier for the hardware to always have the dst, rs1, rs2 in the same places in all instructions, and stores don’t have a dst register so you can use that space for more offset bits.

Most other architectures put the data register in the same place for loads as for stores, despite in one case it’s the destination and in the other case it’s a source.

Thanks Bruce, that is a much better explanation!

As I heard it somewhere, Krste went home one weekend and scribbled on lots of bits of paper, and came up with the current scheme for breaking up immediate/offset fields.

Although they look, frankly, pretty awful to remember and decode by hand, I believe it turns out that any given bit in an immediate or offset can come from only two different places in the instruction, which means you only need a 2:1 mux for each bit, driven by appropriate signals from the opcode. Which makes it, at least, not very expensive for the hardware to unscramble them.

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