Where are the binary blobs?

HiFive Unmatched
1

So … I don’t see a whole lot of people talking about it. The unmatched surely is an achievement, but it’s one I’d like to build on, not rest on. Certainly, something faster would be welcomed. Something with virtual machine support would be welcomed.

But with a certain trepidation, I’m going to ask about the three essential binary blobs (for which, I understand source is not provided for various reasons). To my knowledge, they are:

  1. The DRAM speed training and timing bit
  2. The PCIe speed training and timing bit
  3. The PHY for the GigE.

… w.r.t. items 1 and 2, I understand these are, in general, executed pre-boot during the firmware phase … and on the firmware processor. Given it’s description, I rather feel item 3 may still be interposed at runtime, but this is all still exploratory.

My first questions are:

  1. Are these separate items on the firmware SDcard? (if not, can versions be made with them separate?)
  2. Is there interface documentation for the bits they twiddle?
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SiFive provides all sources, though some are obfuscated because the hardware is licensed. There are no binary blobs on the SDcard.

There may be firmware inside some of the licensed chips, e.g. the Asmedia PCIe switch probably has firmware inside it. There might be firmware inside licensed modules on the SoC, like the PCI root. SiFive doesn’t have access to these sources so can’t provide them. And SiFive probably can’t write to them either.

I’m not a DRAM expert, but I don’t think there is any run time DRAM speed training. We just write magic numbers into magic addresses to initialize the DRAM controller. We can’t provide more info because the DRAM controller is licensed. This code is somewhere in u-boot or openSBI. Maybe we would need speed training if we had DRAM sockets on the board?

With PCIe, I think we just use existing drivers. And I think it is the same with the GigE PHY.

If you want info on how to build an SDcard from scratch from sources, I would suggest https://github.com/carlosedp/riscv-bringup/tree/master/unmatched

The only bit of that which isn’t source is the zero stage boot loader which is in a ROM on the SoC. This just reads the boot select switch positions and jumps to a variable address depending on switch positions. The code for this is given in the processor manual. You can dump it with a debugger if you want to verify.

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