What is F type signal in TileLink and about connection btw AXI-TileLink

Archive Freedom E300
1

Hello,

I’m working with Freedom E300 Platform on Arty-7.

I want to connect manually AXI IP with TileLink IP (TLSPIFlash).

There are 2 types of signal in TLSPIFlash. F type and R type.

To understand about tilelink signal type. But I can’t understand F type signal.

In TileLink Doc, F type is Final signals, changing only on the final beat.

In Doc, beat is a clock slice. Then what is final beat??

If anybody knows about connection between AXI and TileLink,

How to connect TLSPIFlash and AXI Protocol??

I/O of TLSPIFlash and AXI IP are shown as below.

module TLSPIFlash(
input clock,
input reset,
output auto_f_in_a_ready,
input auto_f_in_a_valid,
input [2:0] auto_f_in_a_bits_opcode,
input [2:0] auto_f_in_a_bits_param,
input auto_f_in_a_bits_size,
input [7:0] auto_f_in_a_bits_source,
input [29:0] auto_f_in_a_bits_address,
input auto_f_in_a_bits_mask,
input auto_f_in_a_bits_corrupt,
input auto_f_in_d_ready,
output auto_f_in_d_valid,
output auto_f_in_d_bits_size,
output [7:0] auto_f_in_d_bits_source,
output [7:0] auto_f_in_d_bits_data,
output auto_int_out_0,
output auto_r_in_a_ready,
input auto_r_in_a_valid,
input [2:0] auto_r_in_a_bits_opcode,
input [2:0] auto_r_in_a_bits_param,
input [1:0] auto_r_in_a_bits_size,
input [5:0] auto_r_in_a_bits_source,
input [28:0] auto_r_in_a_bits_address,
input [3:0] auto_r_in_a_bits_mask,
input [31:0] auto_r_in_a_bits_data,
input auto_r_in_a_bits_corrupt,
input auto_r_in_d_ready,
output auto_r_in_d_valid,
output [2:0] auto_r_in_d_bits_opcode,
output [1:0] auto_r_in_d_bits_size,
output [5:0] auto_r_in_d_bits_source,
output [31:0] auto_r_in_d_bits_data,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0
);

I/O of AXI IP is

    .m_axi_mem_araddr(),
    .m_axi_mem_arburst(),
    .m_axi_mem_arcache(),
    .m_axi_mem_arlen(),
    .m_axi_mem_arprot(),
    .m_axi_mem_arready(),
    .m_axi_mem_arsize(),
    .m_axi_mem_aruser(),
    .m_axi_mem_arvalid(),
    .m_axi_mem_rdata(),
    .m_axi_mem_rlast(),
    .m_axi_mem_rready(),
    .m_axi_mem_rresp(),
    .m_axi_mem_rvalid(),

Thank you for reading my question.

2

The F and R here have nothing to do with the TileLink spec. There are two TileLink interfaces, one which gives a register-mapped interface consistent with the SiFive SPI documentation. The other gives a memory-mapped read-only interface, useful when running code directly from SPI.

Connecting AXI with TL directly is not possible. You need an adapter. Using the existing adapter will require learning and using Chisel.

3

Thank you very much for your answer!