TileLink outstanding Gets


#1

Hello

Can I issue multiple outstanding ( e.g inflight ) RD transactions with the current version of TileLink? I say “outstanding”, when several Channel A Get requests for the next data block are generated on the following cycle without waiting for confirmation on the Channel D.

I use the latest Rocket repo and trying to do the following:

class GenericRocc1(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes, nPTWPorts = 1) {
override lazy val module = new GenericRoccImp1(this)
override val tlNode = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters(
sourceId = IdRange (0xA,0xB),
name = s"MyCore0")))))
}

// TL access

val addr_mask = 0.U(5.W) // 5 bit mask to allow 32byte block transfers
val wsource = 0xA.U
val rsource = 0xA.U + ptr
val waddr = (req_vpn << pgIdxBits) + (req_offset & addr_mask) // align to 32 bytes
val raddr = ((req_vpn + ptr) << pgIdxBits) + (req_offset & addr_mask) // align to 32 bytes
val a_size = 5.U
val a_data = “h_5555”.U + ptr
val memData = chD.bits.data

val put = edge.Put(wsource, waddr, a_size, a_data)._2
val get = edge.Get(rsource, raddr, a_size)._2

chA.valid := (state === s_tl_wr || state === s_tl_rd)
chA.bits := (Mux(state === s_tl_wr, put, get))

When I run this simulation, I get the following:

Req on the A interface: opc = 4, addr = 80022000, size = 5, data = 0000000000000000
C0: 104365 [0] pc=[008000107e] W[r 0=0000000080022388][0] R[r11=0000000080022388] R[r12=0000000000000000] inst=[00c5f52b] custom1.rd.rs1.rs2 (args unknown)
Req on the A interface: opc = 4, addr = 80023000, size = 5, data = 0000000000000000
Assertion failed: ‘A’ channel Get carries invalid source ID (connected at CrossingHelper.scala:30:80)
at Monitor.scala:65 assert (source_ok, “‘A’ channel Get carries invalid source ID” + extra)

So it fails on the 2-nd outstanding transaction.

Thank you for your help in advance!


#2

The problem is solved.

It was covered in a more detail here: https://github.com/freechipsproject/rocket-chip/issues/1611