Here is the code description of the Supervisor Mode Interrupt in chisel, but I can’t find the corresponding description about reg_mstatus.prv in privileged v1.10, c language or assembly how to trigger this Supervisor mode interrupt? Please
val s_interrupts = Mux(reg_mstatus.prv <= PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie),pending_interrupts & reg_mideleg,UInt(0))