Is Supervisor Timer & Supervisor Software interrupt supported on U54 or FU540


(Fahad Mubeen) #1

I have successfully generated Machine timer and machine software interrupt, but writing software for S-mode I couldn’t find any way to generate a Supervisor timer/software interrupt.

According to RISC-V documentation, to generate an interrupt in Supervisor mode, the appropriate bits needs to be set in interrupt & exception delegation register “mideleg”, which I did, interrupt needs to be enabled in SIE (supervisor interrupt enable register) which I also did. I double checked that the delegation is supported by writing all 1s to “mideleg”. But I couldn’t find any register in U54 manual for generation of Supervisor timer/software interrupt. Writing to MSIP or generates a machine mode software interrupt not supervisor software interrupt. Can supervisor software interrupt be generated in S mode to S mode (delegated) or am I missing something in interrupt generation.

I also saw Uboot code, and observed it relies on Supervisor-binary interface (SBI) provided by openSBI to generate machine mode IPIs by using ecall, even it doesn’t SSI (supervisor software interrupt).

Thanks,
Fahad


(John Fireman) #2

This is also a question I really want to figure out, for me the only way to trriger a S mode time/software interrupt is to set bit in mip


(Fahad Mubeen) #3

Hi @Phantom0308 I am working on an OS port. Here are some of my findings related to this problem.

Uboot code don’t generate supervisor timer or supervisor software, it relies on openSBI bootloader for that interfaced, I debugged Uboot as well. What I have been successful is in generating Supervisor mode exceptions/traps like faults, UserMode ECall gets routed to supervisor mode, but Timer/Software don’t routed, except for setting sip bit.

For external interrupts, some other details are, the Qemu model has U54 core which has same interrupt enable register for MS-mode in PLIC, even the external mode interrupts don’t get routed to S mode they go to Machine mode directly for Qemu. Even if they are delegated.

But unlike QEMU the Unleashed board has U54-C000 core, which is slightly different from U54, it has separate interrupt enables for M & S mode in PLIC. On hardware board the external interrupts do go to S mode (if they are deleted, and appropriate setting are done in plic).

cc: @jimw/@Krste