Hi, after looking at SPIKE (riscv-isa-sim) sources I realized Spike does not support no-MMU mode.
Could someone please confirm?
Spike is an ISA simulator. The ISA doesn’t have a no-MMU mode, so it isn’t clear what you are asking about here. Maybe you are trying to run a non-MMU linux kernel on spike and ran into a problem? What exact problem did you run into? I see that qemu has nommu hardware configs that are same as regular hardware configs except missing the S support. Maybe that is what you are asking for? In which case, yes, it does look like there is no equivalent feature in spike.
By the way, asking about spike in a github issue may be more useful than asking about it here. I don’t know if there are any spike experts here.
Thanks for quick response, Jim. I will ask at GitHub.
Just for the record - I’m trying to run ELF payload without PK (that would require some setup code at payload side, of course). However Spike fails at bring up (as far as I see), right at the loading payload to the memory:
terminate called after throwing an instance of 'trap_load_access_fault'
#5 0x00007ffff76bbd54 in __cxa_throw () from /usr/lib/x86_64-linux-gnu/libstdc++.so.6
#6 0x00005555555b9b58 in mmu_t::load_slow_path (this=this@entry=0x555555a40c00, addr=67600, len=len@entry=8, bytes=bytes@entry=0x7fffffffc880 "") at ../riscv/mmu.cc:140
#7 0x00005555555ac114 in mmu_t::load_uint64 (addr=<optimized out>, this=<optimized out>) at ../riscv/mmu.h:121
#8 sim_t::read_chunk (this=<optimized out>, taddr=<optimized out>, len=<optimized out>, dst=0x7fffffffc8b0) at ../riscv/sim.cc:312
#9 0x0000555555783f40 in memif_t::write (this=0x7fffffffcaf0, addr=65536, len=<optimized out>, bytes=0x7ffff7ff3000) at ../fesvr/memif.cc:65
#10 0x000055555578cbcb in load_elf[abi:cxx11](char const*, memif_t*, unsigned long*) (fn=<optimized out>, memif=memif@entry=0x7fffffffcaf0, entry=entry@entry=0x7fffffffd658) at ../fesvr/elfloader.cc:87
#11 0x0000555555780a2d in htif_t::load_payload (this=0x7fffffffd640, payload="stream.elf", entry=0x7fffffffd658) at ../fesvr/htif.cc:119
#12 0x0000555555781818 in htif_t::load_program (this=0x7fffffffd640) at ../fesvr/htif.cc:124
#13 0x000055555577fdf9 in htif_t::start (this=0x7fffffffd640) at ../fesvr/htif.cc:81
#14 0x0000555555780c8d in htif_t::run (this=0x7fffffffd640) at ../fesvr/htif.cc:184
#15 0x000055555559338b in main (argc=<optimized out>, argv=<optimized out>) at ../spike_main/spike.cc:384
I tried to avoid translation of vaddr to paddr in mmu_t::translate (by instantiating mmu_t() with proc=NULL for every hart). It didn’t help. Looks like I’m still missing smth or Spike would always use TLB translation to pass virtual to physical to host memory path.
That’s my fault. Be default, memory is mapped at 0x80000000, so ELF payload used instead of PK should be linked and rebased accordingly.
There is an ISA testsuite that uses spike that can be found in github.com/riscv/riscv-tests. It has support code to initialize just enough of the machine so that it can run ISA tests. You might find some useful examples of how to run bare metal code on spike there. See for instance RVTEST_CODE_BEGIN in env/p/riscv_test.h. And see isa/rv64ui/addi.S as an example test for the addi instruction. There are also linker scripts here.
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