Spike execute extra instructions before reset vector

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1

This is the trace of a RISC-V compliance test. The reset vector address is at 0xffffffff80000000
but spike starts at 0x1000 and execute a few instructions before the reset vector.

I cannot find these instructions in the *.elf file, so I assume they are build -in spike, is it true?
Also, is there any way I cannot skip them and start from reset vector?

I run the same *.elf with OVPsim and it starts from reset vector directly.

core 0: 0x0000000000001000 (0x00000297) auipc t0, 0x0
core 0: 3 0x00001000 (0x00000297) x 5 0x00001000
core 0: 0x0000000000001004 (0x02028593) addi a1, t0, 32
core 0: 3 0x00001004 (0x02028593) x11 0x00001020
core 0: 0x0000000000001008 (0xf1402573) csrr a0, mhartid
core 0: 3 0x00001008 (0xf1402573) x10 0x00000000
core 0: 0x000000000000100c (0x0182a283) lw t0, 24(t0)
core 0: 3 0x0000100c (0x0182a283) x 5 0x80000000 mem 0x00001018
core 0: 0x0000000000001010 (0x00028067) jr t0
core 0: 3 0x00001010 (0x00028067)
core 0: 0xffffffff80000000 (0x04c0006f) j pc + 0x4c
core 0: 3 0x80000000 (0x04c0006f)
core 0: 0xffffffff8000004c (0xf1402573) csrr a0, mhartid
core 0: 3 0x8000004c (0xf1402573) x10 0x00000000
core 0: 0xffffffff80000050 (0x00051063) bnez a0, pc + 0
core 0: 3 0x80000050 (0x00051063)

2

At power on, a rocket chip core jumps to a mask rom at 0x1000, executes a couple of instructions, and then branches to the zero stage boot loader. This can’t be disabled in the hardware. I don’t know about spike. In qemu, this is part of the rocket chip core emulation. See for instance

Since you have a spike question, you could try filing an issue against the spike github tree.

3

Thanks

4

I keep forgetting that the forums mangle text. Here is the URL again

https://git.qemu.org/?p=qemu.git;a=blob;f=hw/riscv/sifive_u.c;h=2f19a9cda2ef1c8a23e120cece66be7af0885de1;hb=HEAD#l525