Can anyone tell me the meaning of this log which spike generates?

Archive RISC-V
1

I try to use spike to simulate risc-v.
I generate a log of execution by enter spike -l pk test.riscv.
The log is as follows:
: core 0: 0x0000000000001000 (0x00000297) auipc t0, 0x0
: core 0: 0x0000000000001004 (0x02028593) addi a1, t0, 32
: core 0: 0x0000000000001008 (0xf1402573) csrr a0, mhartid
: core 0: 0x000000000000100c (0x0182b283) ld t0, 24(t0)
: core 0: 0x0000000000001010 (0x00028067) jr t0
: core 0: 0x0000000080000000 (0x1e80006f) j pc + 0x1e8
: core 0: 0x00000000800001e8 (0x00000093) li ra, 0
: core 0: 0x00000000800001ec (0x00000113) li sp, 0
: core 0: 0x00000000800001f0 (0x00000193) li gp, 0
: core 0: 0x00000000800001f4 (0x00000213) li tp, 0
: core 0: 0x00000000800001f8 (0x00000293) li t0, 0
: core 0: 0x00000000800001fc (0x00000313) li t1, 0

“0x00000093” represents “li ra, 0”, “0x00000000800001e8” represents what?

Another question that puzzles me is that the first assemble code I write is li x1, 1; add x4, x1, x2; add x5, x4, x3;
However, the log shows that the first assemble code executed is “auipc t0, 0x0”

2

It’s hard to reproduce what you’re seeing without the input file (either binary or assembly or both), but to try to answer your questions:

It appears that the output of spike’s log in this case is the Core # followed by that core’s Program Counter, followed by the instruction (in parentheses), then the disassembly of that instruction.

As for why the first code you write isn’t the first one that’s being run, it’s very common for system simulators like spike to run instructions before the user program being simulated. Things like setting up the stack, frame, etc., just like in a “c” program there is code that runs before main() gets called. I hope this helps.

3

The log file shows that the following error was reported when executing the memory access instruction.

core 0: exception trap_store_page_fault, epc 0x0000000010000adc
core 0: tval 0x0000000010008c78

Do I need to add a memory model？

4

When a rocket chip core powers on, it first runs a few instructions from the boot rom, which then jumps to the bootloader/OS. Since you are using pk as the OS, the next instructions are all from pk. There will be quite a few instructions from pk while it effectively boots, and then if that is successful (which it should be), only then will your test.riscv start to execute. Since I don’t know what is in test.riscv I can’t say why that might have failed. Is this a regular linux executable? pk can only run statically linked linux applications. You can tell when you go from pk to your app as the pc address range will change. If your app makes a system call, you will end up back in pk. When the system call finishes, you will end up back in your app.

5

when I write csr instruction in crs.S, spike can not recognize the instrcuction.
What’s wrong?

6

You haven’t provided any useful info, such as the instruction you are using and what spike is doing with it.

7

This is a part of my crt.S file.
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10,0
li x11,0
li x12,0
li x13,0
li x14,0
li x15,0
li x16,0
li x17,0
li x18,0
li x19,0
li x20,0
li x21,0
li x22,0
li x23,0
li x24,0
li x25,0
li x26,0
li x27,0
li x28,0
li x29,0
li x30,0
li x31,0
li t0, MSTATUS_FS | MSTATUS_XS | MSTATUS_MIE | MSTATUS_MPIE
csrs mstatus, t0

The result of the disassembly is as follows:
10000000: 4081 li ra,0
10000002: 4081 li ra,0
10000004: 4101 li sp,0
10000006: 4181 li gp,0
10000008: 4201 li tp,0
1000000a: 4281 li t0,0
1000000c: 4301 li t1,0
1000000e: 4381 li t2,0
10000010: 4401 li s0,0
10000012: 4481 li s1,0
10000014: 4501 li a0,0
10000016: 4581 li a1,0
10000018: 4601 li a2,0
1000001a: 4681 li a3,0
1000001c: 4701 li a4,0
1000001e: 4781 li a5,0
10000020: 4801 li a6,0
10000022: 4881 li a7,0
10000024: 4901 li s2,0
10000026: 4981 li s3,0
10000028: 4a01 li s4,0
1000002a: 4a81 li s5,0
1000002c: 4b01 li s6,0
1000002e: 4b81 li s7,0
10000030: 4c01 li s8,0
10000032: 4c81 li s9,0
10000034: 4d01 li s10,0
10000036: 4d81 li s11,0
10000038: 4e01 li t3,0
1000003a: 4e81 li t4,0
1000003c: 4f01 li t5,0
1000003e: 4f81 li t6,0
10000040: 0001e2b7 lui t0,0x1e
10000044: 0882829b addiw t0,t0,136
10000048: 3002a073 csrs mstatus,t0

I use spike to simulate this program, I got an error.
z 0000000000000000 ra 0000000000000000 sp 0000000000000000 gp 0000000000000000
tp 0000000000000000 t0 000000000001e088 t1 0000000000000000 t2 0000000000000000
s0 0000000000000000 s1 0000000000000000 a0 0000000000000000 a1 0000000000000000
a2 0000000000000000 a3 0000000000000000 a4 0000000000000000 a5 0000000000000000
a6 0000000000000000 a7 0000000000000000 s2 0000000000000000 s3 0000000000000000
s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000
s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000
t3 0000000000000000 t4 0000000000000000 t5 0000000000000000 t6 0000000000000000
pc 0000000010000048 va 000000003002a073 insn 3002a073 sr 8000000200046020
An illegal instruction was executed!

spike can’t execute csrs mstatus, t0 instruction.

8

Did you run your code using “spike” or “spike pk”?

If you use “spike pk” then pk is acting as a pseudo operating system which runs in machine mode, and your code is run in user mode.

mstatus is a csr that can’t be accessed from user mode.

If you run spike without pk then your code is the OS and needs to initialize everything itself.

9

The “spike pk” command I used before will report that the csr command cannot be recognized.

I use “spike” to run code, spike reports that “terminate called after throwing an instance of ‘trap_store_access_fault’”. Then I add “-m2048” option to provide memory, but it didn’t work.

10

As Bruce mentioned, spike gives you bare metal. If you want to access memory, then you need to set up the pmp registers to enable memory access. And you need to set up a trap handler to handle errors. See for instance how github.com/riscv/riscv-tests work. The file https://github.com/riscv/riscv-test-env/blob/4d4a4352f4dbd8149af956e30579d9e14860a5a7/p/riscv_test.h has macros to help set up a machine to do basic work. Though you should probably build some example programs and look at how they work. There are a lot of tests for specific ISA or hardware features.

Also, as Bruce mentioned, if you use spike pk, then you can only run user code, and user code can’t write mstatus.

11

thanks, I will try it.