SoC FPGA SiFive E24 Implementation

Hi, I’m trying to create a basic SoC with an E24 core, an UART. I’m using to do it the block design of vivado 2019.1. I have added the E24 as a rtl module to the block design, and I have problems to connect the AHB ports to the vivado AHB-AXI IP Core because I don’t know which AHB port is for instruction cache, data cache and data peripherals.

This is the basic SoC and I would like to change the BonFire Core for a E24 Core.

Hi Pablo, The manual and user guide for the evaluation version of the E24 describe the ports. The only port that’s not directly used for core instructions and data is the front port so system port and peripheral port can be used directly for core instruction and data. Note that there is no instruction or data cache in the evaluation version of E24.