Reading and writing mechanism of QSPI in hifive fu540 board

Hello, all

I have some questions about flash reading and writing.
The code in funciton sifive_spi_transfer_one in spi-sifive.c of Linux :

static int
sifive_spi_transfer_one(struct spi_master *master, struct spi_device *device,
struct spi_transfer *t)
{
struct sifive_spi *spi = spi_master_get_devdata(master);
int poll = sifive_spi_prep_transfer(spi, device, t);
const u8 *tx_ptr = t->tx_buf;
u8 *rx_ptr = t->rx_buf;
unsigned int remaining_words = t->len;

while (remaining_words) {
	unsigned int n_words = min(remaining_words, spi->fifo_depth);
	unsigned int i;

	/* Enqueue n_words for transmission */
	for (i = 0; i < n_words; i++)
		sifive_spi_tx(spi, tx_ptr++);

	if (rx_ptr) {
		/* Wait for transmission + reception to complete */
		sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,
				 n_words - 1);
		sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM, poll);

		/* Read out all the data from the RX FIFO */
		for (i = 0; i < n_words; i++)
			sifive_spi_rx(spi, rx_ptr++);
	} else {
		/* Wait for transmission to complete */
		sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM, poll);
	}

	remaining_words -= n_words;
}

return 0;

}

Can I understand the code in this way ----

If reading QSPI, I need to write the same amount of data to TX FIFO before reading RX FIFO.
If writing, just write TX FIFO directly.

In other words, if currently send the read status command(0x05) for flash, the operation flow here will be :

  1. Write the read status command (0x05) to TX FIFO.
  2. Write the data with the same length as the obtained state to TX FIFO, generally 1 byte.
  3. Read RX FIFO status data, 1 byte.

For flash command without return value, the processing flow is
Write the command to TX FIFO.
If there have address, write it to TX FIFO.

The process of reading flash data is

  1. Write flash read command to TX FIFO
  2. Write address data to TX FIFO
  3. Write 0xff data of the same length as the number of dummy cycles to TX FIFO
  4. Write 0xff data of the same length as read data to TX FIFO
  5. Read the corresponding flash data from RX FIFO

The process of writing flash data is

  1. Write flash write command to TX FIFO
  2. Write address data to TX FIFO
  3. Write data to TX FIFO

Is my understanding correct ?

If not, what is the correct mechanism for QSPI reading and writing ?

Thanks,
Song