I hope this post is acceptable use of the forum. I’ve been invited to join these forums, and thought I’d say hello. My name is Samuel A. Falvo II, and I’m the founder, maintainer, and developer of the Kestrel Computer Project. I work with RISC-V technology on a hobby basis at present, and hope someday to find my niche in the open-hardware / open-source hardware movement.
Current RISC-V activities include working on Polaris, the hardware reiification of the Kestrel-3 emulator’s virtual CPU. The result will sport a 64-bit datapath, hopefully run at 6 MIPS performance (average), and yet still be small enough to fit in an iCE40HX-4K FPGA. It’s M-mode only (no S/U-modes!), no memory protection features, and pretty much just a stock, uninteresting CPU otherwise. I often compare it to a 64-bit Z-80 or 6502.
It’s written by hand in Verilog and my own productivity tool called SMG (State Machine Generator, a misnomer, but don’t know what else to call it). Preliminary synthesis and timing analysis using Yosys suggests an iCE40HX-4K ought to be able to support up to a 28 to 32MHz clock, giving it a performance somewhere in the vicinity of 7 to 8 MIPS. Hopefully, the design will still meet its performance goal when I’m finished; I haven’t checked in a while.
I’m most active on Twitter (@SamuelAFalvoII; warning: this is a personal account, and I often gripe about day to day stuff. I also retweet a lot of things, often involving cats on the Internet. If you don’t want to follow me because of excessive traffic, I understand completely!) and on Hackaday.io.