Openocd jtag incorrectly finds auto0 tap

Archive RISC-V
1

I’m working on a FPGA based RISCV/Debug Module and I’m having trouble with openocd correctly finding my FPGA based JTAG tap controller. Using chipscope in the FPGA I detect a Bypass and IDCODE access to my TAP. The openocd reports the correct IDCODE from the FPGA. Then openocd says its trying to access a tap called auto0.tap, declares that it doesn’t have a IDCODE register, and eventually tries to the read the DTM Control and Status register (I think in the auto0.tap since my tap never reports the 0x10 instruction).

I think the problem is this accessing of the unknown auto0.tap, and I don’t understand why openocd is trying to access it. Has any one else seen this problem?

Thanks,

2

I’m using OpenOCD compiled from source on a Raspberry Pi, and it is from the GitHub RISC-V OpenOCD port. I have GPIO set up on the raspberry pi, for the JTAG connection to an FPGA dev board. Again, it can correctly read out my RISC-V CPU’s IDCODE. After that it thinks it finds a second TAP, but I only have one.
Here is the OpenOCD verbose log file: https://pastebin.com/RUXTbxC1
Here are the two config files:
https://pastebin.com/VhdQCcmd (raspberry pi GPIO config)
https://pastebin.com/AzXATcA0 (riscv ‘top level’ config file).
Thanks for any help or advice you may provide.