Is it technically possible to replace a "Custom Accelerator" with an FPGA?


#1

Hello SiFive team,

I’m wondering to know if it is technically possible to replace the a “Custom Accelerator” with something like “eFPGA” (from “Achronix”) and expose it to OS/user?

Regards,
Manili

P.S. What I mean by “Custom Accelerators” is here at the end of page 1.


(Bruce Hoult) #2

If someone was a customer of Achronix and wanted to integrate a block from them with a SiFive core that would I think be technically possible, but the work required (and cost) might be considerably more than for a standard “Custom Accelerator”.

For a start, in addition to getting data into and results out of the FPGA part (which might fit into the processor pipeline as a custom ALU instruction, or might be better as memory-mapped registers), you’d need some more memory-mapped registers or other interface for programming the FPGA.

I’m just a simple programmer, but that looks like a major custom project to me. Though nowhere near as big as SiFive designing their own FPGA :slight_smile:

@DrewatSiFive @terpstra


#3

@bruce thanks a lot for the reply.

Well, to be honest there is an idea for awhile in my mind:

Using runtime customizable accelerators.

I’m thinking about an idea to replace “Custom Accelerators” with a reconfigurable FPGA (e.g. eFPGA), store some useful IP Core bitstreams (e.g. DSP, BRAM, Hashing, De/Encryption, Gb Networking and so on …) in storage, and let the compiler/OS decides what kind of accelerator this program needs. So when the application is running by the processor it asks the FPGA part to prepare himself for proper acceleration.
I don’t know if my idea technically possible. But I’m pretty sure that if it’s possible to implement it, the only option is RISC-V and Freedom U500 platform.

I’d be very pleased to know your comments about the idea and it’s possibilities …


(Wesley W. Terpstra) #4

You can already do this by using an FPGA connected to the HiFive Unleashed via the FMC connector. Putting the FPGA in-package or in-die will not yield much more performance than you can already achieve with the two-dies-connected-by-chiplink approach that’s already available.

The software aspect you described does not exist, though, so get hacking! :slight_smile:


#5

@terpstra thanks a lot for the reply.

That’s amazing, is it also theoretically/experimentally proved that performance of an in-die FPGA is almost the same as an off-chip one (connects to the chip using Chip-Link)? I’m asking this because I’ve heard about a project at Intel which is an effort to bring the FPGAs in-die and put them beside the CPUs.

AFAIU ASPIRE Lab was about these things (breaking an application into some parent categories and use ASIC for that type of category to accelerate the application). Would you mind correct me if I’m wrong, please?


(Wesley W. Terpstra) #6

Let me clarify. There will, of course, be higher bandwidth and lower latency between the CPU and FPGA if the FPGA were in-die. ChipLink latency is around ~100ns vs. probably like ~25ns for an in-die solution. However, if your accelerator has a reasonably large kernel, it will not make much difference. Your off-chip in-FPGA accelerator can already cache shared memory in the FPGA with the existing system.

There have been lots of people who have tried to tool software to extract parts which can run on an FPGA accelerator. However, none of those efforts have been merged into projects that are running on the HiFive Unleashed.


#7

OK got it, thanks a lot.

My last question, if you are pointing to projects other than the ones in ASPIRE Lab, would you mind mention some of them, please?

Thanks a lot.