@bruce thanks a lot for the reply.
Well, to be honest there is an idea for awhile in my mind:
Using runtime customizable accelerators.
I’m thinking about an idea to replace “Custom Accelerators” with a reconfigurable FPGA (e.g. eFPGA), store some useful IP Core bitstreams (e.g. DSP, BRAM, Hashing, De/Encryption, Gb Networking and so on …) in storage, and let the compiler/OS decides what kind of accelerator this program needs. So when the application is running by the processor it asks the FPGA part to prepare himself for proper acceleration.
I don’t know if my idea technically possible. But I’m pretty sure that if it’s possible to implement it, the only option is RISC-V and Freedom U500 platform.
I’d be very pleased to know your comments about the idea and it’s possibilities …