How to delay 2 `corectrlclk` cycles?

After setting a particular register, the manual indicates the code must wait 1 ddrctrlclk cycle. My coreclk is set to ~1GHz and my ddrctrlclk is set to ~600MHz, meaning a delay of 2 coreclk cycles is required.

Immediately, two nop instructions come to mind.

nop pseudoinstruction appears to be implemented as addi zero, x0, x0. Can the fu740 execute two nops in < 2 clock cycles (i.e. can it exceed 1 IPC for these two pseudoinstructions)?

Hi U007D,

You’re right - the U74 is dual-issue. It can issue two integer ALU operations and they can retire
concurrently. The two ADDI instructions might not be dual-issued (depending on what precedes them in the pipeline), but you can use four ADDI instructions to be safe.


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Awesome, thank you.

I went with the additional overhead of counting mcycles in a loop. It probably means I can’t delay for less than ~10 clock cycles or so, but beyond that minimum, the sky’s the limit, and I won’t need to worry about things like dual issue.

Much appreciated!