HiFive Unleashed Documentation is Here

Firstly, thanks for your detailed comments on the spec. We have not posted here, but we have been including your corrections for the next revision.

As to your specific concern wrt. the UART, you are correct that tlclk is the clock which is divided by div_int. You may also be correct that the reset value is 289 (I’ve not checked). However, the chip has a TLCLKSEL pin which allows you to set tlclk to either hfclk or hfclk/2, so there is no way to pick a value on reset that works for all cases. The ZSBL inspects this pin when it configures div_int on power up.