E300 Boot Procedure

Archive Freedom E300
1

I apologize for what is probably a simple question, but I am having trouble understanding the boot process for the E300 board. I assume that when the board is powered up the EEPROM or OTP or SRAM tells the FPGA to get the program data from the SPI Flash, and I read something about the code being located at 0x20004000.

So as I understand it the basic steps are:

  1. Apply power
  2. FPGA configures itself into a E3 Core Complex from the SPI Flash since the FPGA itself is volatile
  3. The E3 Core then goes to 0x20004000 and looks for a program (say, a “Hello World” program for example)
  4. The program then starts to run

Is that even remotely correct? And what are the specific details I am missing from the process?

Thanks in advance!

2

Hi, Sean.

You are basically correct.

There are one step to add.

  1. FPGA configures itself into a E3 Core Complex from the SPI Flash since the FPGA itself is volatile

2.5. run “bootrom/xip/xip.S” to jump to 0x20004000=XIP_TARGET_ADDR(define in bootrom/xip/Makefile)

  1. The E3 Core then goes to 0x20004000 and looks for a program
3

I think you’ll find that the program start address is the same as the HiFive1, 0x20400000, not 0x20004000. That is, 4 MB after the start of the SPI, not 16 KB.

4

So what loads the bootrom/xip/xip.S into the FPGA?

5

xip.S is converted to rom.v Verilog file in freedom/bootrom/xip/Makefile

romgen := $(BUILD_DIR)/rom.v
$(romgen): $(hex)
	$(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@

So, xip.S is load at following.

2. FPGA configures itself into a E3 Core Complex from the SPI Flash since the FPGA itself is volatile
6

OK, I understand now. Thank you so much for your help in clearing that up for me! Thanks to you also Bruce for pointing out the correct address.