From the already published EIC7700X Datasheet, looks like we have 4x U84 cores (main CPU cluster, MCPU) and another 2x E31 cores, one for security (SCPU) and the other for low power (LCPU). I’d like to see the topology among them being documented, specifically:
Memory map from each processor’s view
Are they cache coherent?
Interconnect among them: mailbox, interrupt routing with diagram.
Also I’m a little bit confused by the boot flow section in the datasheet. In the P550 board I got, Boot-SPI contains DDR init + secondary boot + opensbi/uboot payload. It looks like these components are assembled by the nsign tool.
In the configuration file passed to nsign:
There is a field to dictate where the bootchain module is to be loaded and run (SCPU/MCPU…) How is this selection related to the boot_sel pin values? Am I correct to assume it’s always the SCPU that starts execution first and run from the ROM? Then based on the boot_sel and boot_flags in the header, it will load up different bootchain modules and kickstart the MCPU? Please help clarify this part.
BTW, any guidance on JTAG? I’m using openOCD to connect to JTAG0, but I only see the MCPU being discovered. Datasheet says JTAG0 should cover MCPU, LCPU and NPU. How to discover all of them? For JTAG1, can I just connect a FT2232 to the pins and start debugging? Any special settings I need to jtag the SCPU?
Hi Bo,
Have you checked EIC7700X datasheet section 3.3 and 3.9 for the memory map and interrupt questions? Are they helpful?
Regarding the JTAG questions, current boards that already delivered to users have issues on using JTAG, the new batch will have it fixed. More detailed info will be posted on SiFive’s web, you can contact and request board swap at that time. And more guidance will be released later as well.
Unfortunately they are not very helpful. Section 3.3 sounds like a very general introduction to the U84/E31 cores and it lacks the context of the SoC. I’d like to see something like section 3.5, which details the memory map for MCPU, but for all other SCPU/LCPU… components. For interrupts, do you have a diagram of how different devices interrupts are routed to SCPU/MCPU/LCPU? And again are they cache coherent?
Also any answer regarding the boot process question?
The cores inside the MCPU are cache coherent among each other. However, MCPU, LCPU, SCPU are not cache coherent with each other.
You can refer to Section 3.4 for a list of interrupts for each CPU.
You can config the interrupt route from TOP CSR :
I guess I’ll just wait for your next release of the EIC7700X datasheet. I don’t know what you mean by TOP CSR. The current version of datasheet has no mentioning of it, except for PCIe Top Csr register space, which I assume is not related. I hope this can be further clarified in the next release, along with the memory map and boot process related questions. Thanks.
