I don’t think there’s any intention that ChipLink be secret – quite the opposite, I’d think. I’d say it’s more a matter of the people who know about this being spread thinly and while the company is expanding quickly it takes time to bring new people (like me) up to speed. And I’m not a hardware guy anyway.
As far as I know, the interface to the MicroSemi board is exactly the same as to the VC707 and nothing changes on the HiFive Unleashed side. However I’ve not personally set either one up.
I just tried entering “sifive chiplink” into google and one of the first results was https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/chiplink/ChipLink.scala
You can go up one level and find more.
It’s not documentation, but it is HDL source, albeit not Verilog.