Dear RISC-V developers,
I am happy to announce Mecrisp-Quintus, a native code Forth for RV32IM instruction set written entirely in assembler. It is available in the download area of mecrisp.sourceforge.net
Its first targets are Picosoc by Clifford Wolf on a Lattice HX8K FPGA breakout board, and the LM4F120 Stellaris Launchpad, as I wrote an emulator called Mamihlapinatapai which allows to run RV32IM opcodes on ARM Cortex M3/M4.
Now, it is time to support real RISC-V hardware. It is difficult for me to find an HiFive1 here in Germany, therefore, I am looking for help. Is there a Forth freak who has hardware available and wishes to help ? Technically, a bare metal UART echo written in plain assembler is necessary to port Mecrisp-Quintus to a new piece of hardware, along with adjustments to the memory map.
If you are interested, just drop me a line. I am available for assistance.
Best wishes from Germany and hats off to the SiFive team,