ganboing
September 23, 2025, 7:22am
1
Hi Sifive/ESWIN,
Would you mind clarify how to boot from UART? What I’ve done so far:
Grab the nsign configuration file used to generate the bootloader blob: meta-sifive/recipes-bsp/bootchain/files/nsign.cfg at rel/meta-sifive/hifive-premier-p550 · sifiveinc/meta-sifive · GitHub
Apply the following patch:
--- a/nsign.cfg 2024-11-13 16:46:57.239713067 -0800
+++ b/nsign.cfg 2025-05-02 20:25:27.746613201 -0700
@@ -1,5 +1,5 @@
- cmd=chief_sign
- out=bootloader_ddr5_secboot.bin
+ cmd=uart_sign
+ out=bootchain.ihex
Generate the bootchain.ihex with the ddr_fw.bin and second_boot_fw.bin from sifive repo.
The ihex can be successfully generated. However, with the board in UART boot, and transfered the ihex via minicom ascii mode, the boot failed. SCPU reported the followin:
exception occur:
mcause = 0x00000007
mepc = 0x58017840
mtval = 0x00000000
It seems like a NULL pointer dereference to me. Please let me know if there’s anything I missed. Thanks!
ganboing
October 15, 2025, 4:25pm
2
Raza sent me the correct nsign config, and I can do UART boot now:
## HiFive P550 UART Boot Guide
Some background regarding P550 bootflow. For P550, it's a 1 DIE configuration (EIC7702 is 2 DIE).
Thus, the stock stable bootchain (w/o secure boot) comes only with 3 parts:
- Secondary Boot aka. "FIRMWARE": A tiny blob right after firmware to do basic initialization, such as PLL clock.
- DDR Init aka. "DDR": Blob for initializing DDR memory. ~200KB.
- U-Boot/OpenSBI payload aka. "BOOTLOADER": The actual bootloader.
These parts are packaged in a container image (bootchain) with ESWIN custom format that's similar to tar/cpio.
The program `nsign` is used to generate such container image. For each component in the image, there's
also metadata to describe its type FIRMWARE/DDR/BOOTLOADER, the load and entry point address, and the
CPU (SCPU or MCPU) that's responsible for running it. In regular boot configuration, such image is
flashed to boot SPI, and DIP switches are set to `[0 0 1 0]`. After power-on, the SCPU (32bit) starts
executing Masked ROM, where there's logic to check DIP switch states and parse, then load the blobs
from the bootchain and invoke them in a pre-defined order: FIRMWARE->DDR->BOOTLOADER
For bootloader developers, such as OpenSBI/U-Boot or EDK2, it might be helpful to a. replace the "BOOTLOADER"
at will, and b. start JTAG debugging as early as possible. EIC7700(X)/P550 has the ability to boot from UART.
In UART boot mode, the bootchain image is read from UART, bypassing boot SPI. Hence, there's zero possibility
show original
This is very useful for advanced users like myself who hacks OpenSBI and U-Boot from time to time
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