while working on my own FPGA optimized RISC-V implementation from time-to-time I update the RISC-V toolchain.
BTW: I really enjoyed to read the “All Aboard” blog post series about the toolchain, it helps alot
Today I updated riscv-tools to the current master branch with also updated gcc to commit 65cb174.
Because my design is RV32IM only I usally only compile a 32bit toolchain
Everythings seems to work fine, but when creating a listing of the linked elf I notice that functions seem to be padded/aligned now (look at the “unimp” line in the listing below). It seems that the compiler and/or linker align all functions to a modulo 8 ==0 address. I doesn’t harm anything, besides consuming memory. But is there a possibility to switch it of? I have already tried fno-align-functions, but this doesn’t help.
00010160 <_atoi_r>: 10160: 00a00693 li a3,10 10164: 00000613 li a2,0 10168: 00d0606f j 16974 <_strtol_r> 1016c: 0000 unimp ... 00010170 <__errno>: 10170: 000677b7 lui a5,0x67 10174: bb87a503 lw a0,-1096(a5) # 66bb8 <_impure_ptr> 10178: 00008067 ret 1017c: 0000 unimp ...