Early boot and hart 0: relation between FSBL, opensbi and u-boot

HiFive Unmatched
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Hello,

I’ve been binge-reading every documentation and source code I can get my hands on, and there is something I do not quite understand about the early boot process.
In the FU740-C000 the boot process is described as: ZSBL, then FSBL, then BBL. The ZSBL is in an on-chip ROM and the BBL is implemented by OpenSBI.

But what is the FSBL ? Is it a not-released-yet, or maybe not-upstreamed-yet, source ? I’ve looked into upstream’s OpenSBI’s source code for hints of PLL configuration (which is documented as being part of the FSBL’s job), and the only obvious matches are for another board. I’ve found that the linux kernel seems to have reclocking support for the CPU’s clock generator, but I guess the boot process does not just run on the 26MHz base clock until the kernel takes over.

And beyond the consideration of what does the FSBL’s job, I am trying to understand what the hart 0 is doing once the OS is booted up: as it lacks S-mode I do not expect it to be managed by the OS. Is it doing some monitoring tasks, like checking temperatures and updating fan PWM ? I see that the linux kernel can be configured to run in M mode, would the hart 0 be running linux for its own needs ?

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The BBL (Berkeley Boot Loader) reference is obsolete; it isn’t used anymore. We probably shouldn’t have software info in a hardware document. We are working on better software docs, but in the meantime I would suggest this reference
riscv-bringup/unmatched at master · carlosedp/riscv-bringup · GitHub

I believe that hart 0 gets put in a WFI (wait for interrupt) loop, and the interrupt never comes because we never allow one to reach it. I don’t know the details though, I’m not an expert on the boot process.

The patches needed to boot the unmatched can be found on github in sifive/meta-sifive. We are actively upstreaming patches, but the review process can take some time.

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Awesome ! So it’s a first u-boot which then runs OpenSBI and a second u-boot.

No worry, having a reasonable hope that it will get upstream eventually is enough for me :slight_smile: . And if the code gets improved in the process, all the better.

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Here is a very nice overview to the boot process: FOSDEM 2020 - RISC-V bootflow: What’s next ?.

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