On the face of it that’s a stupid question, (so should be easy to clear up) as the reference manual clearly states:
“The configurable E31 RISC-V Coreplex provides a high-performance single-issue in-order 32-bit
execution pipeline, with a peak sustained execution rate of one instruction per clock cycle.”
So it’s clearly a 32 bit Arch. But the document riscv-compressed-spec-v1.7.pdf states:
C.SD is an RV64C/RV128C-only instruction that stores a 64-bit value in register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to sd rs2′, offset7:3.
So that C.SD instruction, which expands to sd rs2… is 64/128 bit only. But the compiler produces that instruction for my LoFive board, which is 32bit?
main: addi sp,sp,-32 sd s0,24(sp) addi s0,sp,32
Perhaps I’ve got the wrong version of that compressed document. I’m not very proficient at assembly so perhaps I’m mis-reading both documents. Actually that first 3 lines of assembly in my main() strike me as a strange, back to re-reading the compressed-spec