# What is PLIC interrupt source start and end in interrupt source mapping?

**URL:** <https://forums.sifive.com/t/what-is-plic-interrupt-source-start-and-end-in-interrupt-source-mapping/5705>\
**Category:** HiFive1 Rev B\
**Created:** [May 3, 2022, 11:44am UTC](https://forums.sifive.com/t/what-is-plic-interrupt-source-start-and-end-in-interrupt-source-mapping/5705 "2022-05-03T11:44:27Z")\
**Posts on this page:** 1\
**Showing post:** 9

<div class="post-metadata">

**Author:** ![pds](https://avatars.discourse-cdn.com/v4/letter/p/8edcca/32.png) [@pds](https://forums.sifive.com/u/pds)\
**Post date:** [May 18, 2022, 11:05pm UTC](https://forums.sifive.com/t/what-is-plic-interrupt-source-start-and-end-in-interrupt-source-mapping/5705/9 "2022-05-18T23:05:52Z")

</div>

Great to hear @bsvtgc glad all is as expected. Your questions give great inspiration, here is an attempt at answering them.

First, two general ideas to keep in mind:

- Once set up and configured, and the interrupt-triggering event has been determined, there is no need to mess with CSR’s in the external PLIC handlers – this gives great simplification
- Upon `mret`, interrupt will re-trigger endlessly until all enabled devices have been cleared – the device clearing procedures, some are automatic and some are manual, are specific to each device (see below)

**How is CSR `mip.MEIP` set?**  
Whenever `PLIC_PRIORITY[4*source_id] > PLIC_THRESHOLD`, and the specific external device block condition is met.

**How should CSR `mip.MEIP` be cleared?**  
By the three steps of:  
reading the _source id_ value from `CLAIM/COMPLETE`;  
clearing the specific external device block condition; and  
writing the _source id_ value back to `CLAIM/COMPLETE`;  
in that order.

**How is an external interrupt enabled?**  
_By the four general conditions_:  
CSR `mstatus.MIE` = 1  
CSR `mie.MEIE` = 1  
`PLIC_ENABLE[4 * (source_id / 32)].[source_id % 32]` = 1  
`PLIC_PRIORITY[4 * source_id]` \>= `PLIC_THRESHOLD`  
_and, depending on the source id, one of the following specific conditions_:  
**gpio** : bit _n_ of `input_en` is 1; bit(s) `n` of `rise_ie`, `fall_ie`, `high_ie`, and/or `low_ie` are 1; bit _n_ of `input_val` is 1 (either by outside electrical connection, or by bit _n_ of `output_en` and `output_val` both being 1, with tri-state or no outside electrical connection); and bit _n_ of `iof_en` is 0.  
**pwm** : `pwmcount` \>= `pwmcmp`  
**spi** : (`txfifo` \< `txcnt`) || (`rxfifo` \> rxcnt)  
**uart** : (`txfifo` \< `txcnt`) || (`rxfifo` \> `rxcnt`)  
**i2c** : …  
**aon rtc** : rtcs \>= rtccmp  
**aon wdog** : wdogtime \>= wdogcmp  
**aon pmu** : …

**How do the three different levels of interrupt pending bits all relate?**  
CSR `mip.MEIP` – is the cumulative (i.e., inclusive-or’d) result of all external sources;  
PLIC core pending bits for each source id – are the individual results of each external device block source;  
GPIO block pending bits – are one of the many PLIC core sources, when the corresponding pin multiplexer bit of `IOF_EN` is 0. Note that the GPIO block pending bits are unavailable and inaccessible when other external device blocks have been routed to the output pins, with the corresponding bit of `IOF_EN` is 1.

**How are the specific device external block pending interrupts cleared?**  
They all have very different interrupt pending and clearing behavior.  
**pwm** : level sensitive only; `ip` cleared automatically when `count` \< `cmp`, or cleared manually when the _sticky_ bit is set and by clearing (i.e., writing 0 to) `ip`.  
**uart** : level sensitive only; `ip` cleared automatically when `txfifo` \>= `txcnt`, and `rxfifo` \<= `rxcnt`.  
**spi** : level sensitive only; `ip` cleared automatically when `txfifo` \>= `txcnt`, and `rxfifo` \<= `rxcnt`.  
**gpio** : edge or level sensitive; `ip` cleared manually by setting (i.e., writing 1 to) `ip`.  
**aon rtc** : level sensitive only; `ip` cleared automatically when `rtccmp` \< `rtcs`.  
**i2c** : as suggested by the Manual, see [opencores i2c](https://opencores.org/project,i2c).

---

_[View the full topic](https://forums.sifive.com/t/what-is-plic-interrupt-source-start-and-end-in-interrupt-source-mapping/5705)._