# Unable to "make upload" to hifive1-revb target **URL:** \ **Category:** Freedom E300\ **Created:** [March 27, 2020, 9:20pm UTC](https://forums.sifive.com/t/unable-to-make-upload-to-hifive1-revb-target/3514 "2020-03-27T21:20:38Z")\ **Posts on this page:** 3\ **Page:** 1
**Author:** ![nlivic](https://avatars.discourse-cdn.com/v4/letter/n/6bbea6/32.png) [@nlivic](https://forums.sifive.com/u/nlivic)\ **Post date:** [March 27, 2020, 9:20pm UTC](https://forums.sifive.com/t/unable-to-make-upload-to-hifive1-revb-target/3514/1 "2020-03-27T21:20:38Z")
Host: ubuntu 19.04 Freedome SDK: latest pull 2020-03-27 JLink: SEGGER v6.70 (with J-Link Pro), tried 3 other versions here Toolchains (gcc, openocd): ubuntu14 these look problematic in the issue below: (0 ProgBuf entries) and autoexec[0] implemented: No i am assuming programming the hifive1-revb would work automatically, but didn’t readily see much information on addressing the below error i am having. Note. e Makefile #TARGET ?= (shell find $(TARGET\_ROOT)/bsp/\* -type d | head -n 1 | rev | cut -d ‘/’ -f 1 | rev) TARGET ?= sifive-hifive1-revb $ make upload scripts/upload --hex /home/nlivic/rv2/freedom-e-sdk/software/hello/debug/hello.hex --jlink JLinkExe SEGGER J-Link Commander V6.70 (Compiled Mar 27 2020 14:37:00) DLL version V6.70, compiled Mar 27 2020 14:36:47 Connecting to J-Link via USB…O.K. Firmware: J-Link V11 compiled Mar 19 2020 11:11:08 Hardware version: V11.00 S/N: 601001907 License(s): RDI, FlashBP, FlashDL, JFlash, GDB VTref=3.303V Device “FE310” selected. Connecting to target via JTAG ConfigTargetSettings() start ConfigTargetSettings() end TotalIRLen = 5, IRPrint = 0x01 JTAG chain detection found 1 devices: #0 Id: 0x20000913, IRLen: 05, Unknown device Debug architecture: RISC-V debug: 0.13 AddrBits: 7 DataBits: 32 IdleClks: 5 Memory access: Via system bus: No Via ProgBuf: No (0 ProgBuf entries) DataBuf: 0 entries autoexec[0] implemented: No Failed to temporarily halt core during identification Attaching to core failed. Trying again with connect under reset (ndmreset-bit) Memory access: Detected: RV32 core CSR access via abs. commands: Yes * * * WARNING: CPU could not be halted * * * ConfigTargetSettings() start ConfigTargetSettings() end ConfigTargetSettings() start ConfigTargetSettings() end \*\*\*\*\*\* Error: Timeout while waiting for core to halt after reset and halt request Communication timed out: Requested 4 bytes, received 0 bytes ! Specific core setup failed. Could not read hardware status! Cannot connect to target. J-Link\>Target connection not established yet but required for command. Device “FE310” selected. Selected interface (JTAG) is not supported by the connected probe. J-Link\>Target connection not established yet but required for command. Device “FE310” selected. Connecting to target via JTAG Cannot connect to target Any advice on what i am doing wrong or alternatives would be much appreciated. thanks! ---
**Author:** ![pds](https://avatars.discourse-cdn.com/v4/letter/p/8edcca/32.png) [@pds](https://forums.sifive.com/u/pds)\ **Post date:** [March 29, 2020, 11:38am UTC](https://forums.sifive.com/t/unable-to-make-upload-to-hifive1-revb-target/3514/2 "2020-03-29T11:38:04Z")
Hi! From the successful detection of the cpu id 0x20000913 it looks like all the hardware is properly connected - a good sign. Take a close look at the `openocd.cfg` file, especially the lines or statements which declare the CPUID and TARGET… parameters. Probably they are some blank or default value, I believe they should be something like ‘riscv’ This should resolve the problem in your log above which shows ‘Unknown device’ rather than ‘SiFive…’ After that, I found best results putting in carefully placed reset delays and wait time - more on that later. Good progress so far! ---
**Author:** ![nlivic](https://avatars.discourse-cdn.com/v4/letter/n/6bbea6/32.png) [@nlivic](https://forums.sifive.com/u/nlivic)\ **Post date:** [March 30, 2020, 2:49am UTC](https://forums.sifive.com/t/unable-to-make-upload-to-hifive1-revb-target/3514/3 "2020-03-30T02:49:41Z")
Hi Paul, thank you for the help. i see with the lastest freedom studio, for my target (bsp/sifive-hifive1-revb/), there is no openocd.cfg, only j-link configuration. while i tried to connect with openocd over SEGGER j-link, there was definitely unsuitable interface config, that i haven’t spent more time on. in this case, i mistakening didn’t have NRST pin floating, which seemed to account for the error above. while putting this pin into this state, i no longer get the halt issue but see the below issue: $ make upload scripts/upload --hex /home/nlivic/rv2/freedom-e-sdk/software/hello/debug/hello.hex --jlink JLinkExe SEGGER J-Link Commander V6.70 (Compiled Mar 27 2020 14:37:00) DLL version V6.70, compiled Mar 27 2020 14:36:47 Connecting to J-Link via USB…O.K. Firmware: J-Link V11 compiled Mar 19 2020 11:11:08 Hardware version: V11.00 S/N: 601001907 License(s): RDI, FlashBP, FlashDL, JFlash, GDB VTref=3.332V Device “FE310” selected. Connecting to target via JTAG ConfigTargetSettings() start ConfigTargetSettings() end Could not measure total IR len. TDO is constant high. ConfigTargetSettings() start ConfigTargetSettings() end Could not measure total IR len. TDO is constant high. ConfigTargetSettings() start ConfigTargetSettings() end Could not measure total IR len. TDO is constant high. ConfigTargetSettings() start ConfigTargetSettings() end Could not measure total IR len. TDO is constant high. Cannot connect to target. J-Link\>Target connection not established yet but required for command. yes timing might be problematic. curious if anyone has a design.dts for the sifive-hifive1-revb target with SEGGER j-link that works? thanks!