# Timer interrupt in E3 coreplex

**URL:** <https://forums.sifive.com/t/timer-interrupt-in-e3-coreplex/76>\
**Category:** Freedom E300\
**Created:** [August 10, 2016, 6:50am UTC](https://forums.sifive.com/t/timer-interrupt-in-e3-coreplex/76 "2016-08-10T06:50:52Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Chuanhua](https://avatars.discourse-cdn.com/v4/letter/c/cdc98d/32.png) [@Chuanhua](https://forums.sifive.com/u/Chuanhua)\
**Post date:** [August 10, 2016, 6:50am UTC](https://forums.sifive.com/t/timer-interrupt-in-e3-coreplex/76/1 "2016-08-10T06:50:52Z")

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In page 14, Section 6.3 of the E3 coreplex manual, there is a sentence as follows:

A timer interrupt is pending whenever the value in a hart’s mtimecmp register is greater than or equal to mtime.

However, in page 8 of Krste’s “Interrupts” presentation, it says “MTIP set when mtime \>= mtimecmp”.

Which one is correct?

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**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\
**Post date:** [August 10, 2016, 5:18pm UTC](https://forums.sifive.com/t/timer-interrupt-in-e3-coreplex/76/2 "2016-08-10T17:18:48Z")

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Thanks for pointing out the discrepancy. Krste’s presentation and the Privileged Spec v. 1.9 are correct: MTIP bit is set when mtime \>= mtimecmp. We will correct the E3 Coreplex manual in the next version.