# Tandem Verification with spike

**URL:** <https://forums.sifive.com/t/tandem-verification-with-spike/1453>\
**Category:** RISC-V\
**Created:** [July 27, 2018, 4:14am UTC](https://forums.sifive.com/t/tandem-verification-with-spike/1453 "2018-07-27T04:14:47Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![aneesh4tvm](https://avatars.discourse-cdn.com/v4/letter/a/848f3c/32.png) [@aneesh4tvm](https://forums.sifive.com/u/aneesh4tvm)\
**Post date:** [July 27, 2018, 4:14am UTC](https://forums.sifive.com/t/tandem-verification-with-spike/1453/1 "2018-07-27T04:14:47Z")

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I am developing a RISC-V core. I was planning to do a tandem verification with spike. My plan is that when an instruction in RTL is getting retired, it has to corss check with spike log (basically destination register value checks).

Presently I am unable to generate a log file from spike (-l with various options I have tried).

Does anybody help me in this.