# Supervisor Mode Interrupts

**URL:** <https://forums.sifive.com/t/supervisor-mode-interrupts/2451>\
**Category:** RISC-V\
**Created:** [June 6, 2019, 7:59am UTC](https://forums.sifive.com/t/supervisor-mode-interrupts/2451 "2019-06-06T07:59:34Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![suzhaow](https://avatars.discourse-cdn.com/v4/letter/s/9e8a1a/32.png) [@suzhaow](https://forums.sifive.com/u/suzhaow)\
**Post date:** [June 6, 2019, 7:59am UTC](https://forums.sifive.com/t/supervisor-mode-interrupts/2451/1 "2019-06-06T07:59:34Z")

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Here is the code description of the Supervisor Mode Interrupt in chisel, but I can’t find the corresponding description about reg\_mstatus.prv in privileged v1.10, c language or assembly how to trigger this Supervisor mode interrupt? Please

val s\_interrupts = Mux(reg\_mstatus.prv \<= PRV.S || (reg\_mstatus.prv === PRV.S && reg\_mstatus.sie),pending\_interrupts & reg\_mideleg,UInt(0))