# Specification Consistency **URL:** \ **Category:** Freedom E300\ **Created:** [February 13, 2019, 7:27am UTC](https://forums.sifive.com/t/specification-consistency/2079 "2019-02-13T07:27:27Z")\ **Posts on this page:** 4\ **Page:** 1
**Author:** ![AmeyaVSingh](https://avatars.discourse-cdn.com/v4/letter/a/82dd89/32.png) [@AmeyaVSingh](https://forums.sifive.com/u/AmeyaVSingh)\ **Post date:** [February 13, 2019, 7:27am UTC](https://forums.sifive.com/t/specification-consistency/2079/1 "2019-02-13T07:27:27Z")
Hello Everyone, I have found multiple issues in the specifications manual for the FE310 Manual available from here: > **[Documentation](https://www.sifive.com/documentation)** > > Manuals, user guides, and other documentation for SiFive's RISC-V Core IP, chips, development boards, and tools. Here is a snapshot of the documentation with revision v2p3 for the SPI Controller on the FE310 SoC. ![RISCVFE310-SPI](https://us1.discourse-cdn.com/flex020/uploads/sifive/original/1X/4a9e852be256413bd425e1dc19d2fb1f75661f38.png) As per the specifications the bit field dir is 1 only for spi0 and zero for spi1 and spi2. But then the text description is not matching with the data on the table 18.15. Should the following text be: > The reset value is 0x0008 0008, corresponding to proto = single, dir = Rx, endian = MSB, and len = 8 for spi0. The reset value is 0x0008 0000, corresponding to proto = single, dir = Rx, endian = MSB, and len = 8 for spi1 and spi2. this: > The reset value is 0x0008 0008, corresponding to proto = single, dir = **Tx** , endian = MSB, and len = 8 for spi0. The reset value is 0x0008 0000, corresponding to proto = single, dir = Rx, endian = MSB, and len = 8 for spi1 and spi2. or this one: > The reset value is 0x0008 0008, corresponding to proto = single, dir = Rx, endian = MSB, and len = 8 for spi0. The reset value is 0x0008 0000, corresponding to proto = single, dir = **Tx** , endian = MSB, and len = 8 for spi1 and spi2. Can anyone help me in this regard? How do I get in touch with SiFive Technical Team to report such issues in the specifications? Thanks in advance. Regards, Ameya Vikram Singh Ameya Vikram Singh | Senior Member of Technical Staff | [CircuitSutra](http://circuitsutra.com/) | +91 8122657508 | _ESL Methodologies: SystemC Modeling IP & Services_ _(We are defining modeling methodologies for RISC-V ecosystem & AI/DL SoC)_ ---
**Author:** ![jimw](https://avatars.discourse-cdn.com/v4/letter/j/f14d63/32.png) [@jimw](https://forums.sifive.com/u/jimw)\ **Post date:** [February 14, 2019, 7:47pm UTC](https://forums.sifive.com/t/specification-consistency/2079/2 "2019-02-14T19:47:08Z")
I filed an internal bug report against the docs. I don’t know if there is any other way for you to report doc bugs. I suppose you could try contacting sales/marketing to try to open a communication channel between the two companies. The SPI I/O Direction table clearly specifies that 0 is Rx and 1 is Tx. So I don’t think that part is wrong. Otherwise, I have no idea what is wrong here. FYI You can find the source for the SPI module in > **[sifive/sifive-blocks](https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi)** > > Common RTL blocks used in SiFive's projects. Contribute to sifive/sifive-blocks development by creating an account on GitHub. ---
**Author:** ![AmeyaVSingh](https://avatars.discourse-cdn.com/v4/letter/a/82dd89/32.png) [@AmeyaVSingh](https://forums.sifive.com/u/AmeyaVSingh)\ **Post date:** [February 15, 2019, 4:27am UTC](https://forums.sifive.com/t/specification-consistency/2079/3 "2019-02-15T04:27:50Z")
Thank you @jimw for the assistance. But there are multiple inconsistencies throughout the documentation. I will try to get in touch with the sales/marketing team. On another note, it would be great if one can have a bug tracker like system for reporting and probable fixes for the documentation team, which can be passed to the technical team for review. That way, many redundant specification inconsistencies/errors requests can be tracked. Best Regards, Ameya Vikram Singh ---
**Author:** ![jimw](https://avatars.discourse-cdn.com/v4/letter/j/f14d63/32.png) [@jimw](https://forums.sifive.com/u/jimw)\ **Post date:** [February 15, 2019, 6:19pm UTC](https://forums.sifive.com/t/specification-consistency/2079/4 "2019-02-15T18:19:31Z")
We have a way for customers/partners to file bug reports. We don’t have a way for the general public to do this, other than via the forums, or via github issues. Unfortunately, the docs aren’t a public github repo, so you can’t file issues there. You could file issues in sifive/sifive-blocks, but that may not be the best place for that.