# Simulator other than VCS

**URL:** <https://forums.sifive.com/t/simulator-other-than-vcs/777>\
**Category:** SiFive RISC-V Core IP Evaluation\
**Created:** [September 25, 2017, 2:31pm UTC](https://forums.sifive.com/t/simulator-other-than-vcs/777 "2017-09-25T14:31:24Z")\
**Posts on this page:** 1\
**Page:** 1

<div class="post-metadata">

**Author:** ![perryman](https://avatars.discourse-cdn.com/v4/letter/p/7c8e57/32.png) [@perryman](https://forums.sifive.com/u/perryman)\
**Post date:** [September 25, 2017, 2:31pm UTC](https://forums.sifive.com/t/simulator-other-than-vcs/777/1 "2017-09-25T14:31:24Z")

</div>

In the Eval User guide there is this disclaimer:

> Requirements  
> The example test simulation environment included in this release is designed to work with Syn-  
> opsys VCS (K-2015.09-SP2). GNU Make is used to build the RTL into a simulator and run the  
> included binary test files.  
> I don’t have access to that. Has anyone successfully compiled this core with Questa or ius/xcelium ?

Ian