# SiFive E31 FPGA Eval Kit - PMP in "U" mode

**URL:** <https://forums.sifive.com/t/sifive-e31-fpga-eval-kit-pmp-in-u-mode/1252>\
**Category:** Freedom E300\
**Created:** [May 29, 2018, 8:39am UTC](https://forums.sifive.com/t/sifive-e31-fpga-eval-kit-pmp-in-u-mode/1252 "2018-05-29T08:39:08Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![Cesare.Garlati](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/cesare.garlati/32/465_2.png) [@Cesare.Garlati](https://forums.sifive.com/u/Cesare.Garlati)\
**Post date:** [May 29, 2018, 8:39am UTC](https://forums.sifive.com/t/sifive-e31-fpga-eval-kit-pmp-in-u-mode/1252/1 "2018-05-29T08:39:08Z")

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Is the U mode actually implemented in the sifive\_coreip\_E31\_FPGA\_Evaluation\_v2p0\_0.mcs?

PMP works as documented in “locked” M mode but seems completely missing in U mode.

Any examples / suggestions / pointers ?

Thanks!

Cesare

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**Author:** ![mhamrick](https://avatars.discourse-cdn.com/v4/letter/m/3ab097/32.png) [@mhamrick](https://forums.sifive.com/u/mhamrick)\
**Post date:** [May 29, 2018, 3:06pm UTC](https://forums.sifive.com/t/sifive-e31-fpga-eval-kit-pmp-in-u-mode/1252/2 "2018-05-29T15:06:09Z")

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Hi Cesare,

Are you saying:  
a. you can’t program the PMP related registers (pmpcfg0 & pmpcfg1) in U mode, or  
b. you can program the PMP related registers in M mode, but they seem to have no effect in U mode?

If a, then it’s working as designed, you can only program them in M mode. If b, then… hmm… it’s my understanding the E31 FPGA Eval is supposed to have all the features turned on. Could you post the values you used to program the registers and what you tried to test them?

-cheers,  
-m

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**Author:** ![Cesare.Garlati](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/cesare.garlati/32/465_2.png) [@Cesare.Garlati](https://forums.sifive.com/u/Cesare.Garlati)\
**Post date:** [May 29, 2018, 4:03pm UTC](https://forums.sifive.com/t/sifive-e31-fpga-eval-kit-pmp-in-u-mode/1252/3 "2018-05-29T16:03:02Z")

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Hi Meadhbh,

Thank you for the prompt reply!

It’s b: I can program the PMP related registers in M mode, but they seem to have no effect in U mode.

There are no particular values to post: any settings I try work as described in v 1.10 with the “L” bit set. If the L bit is not set the very same settings are completely ignored both in M mode (as expected) and in U (not expected).

For the benefit of the forum, it would be probably be more instructive if you could share SiFive test cases showing PMP functionality working in U mode?

Thanks!

Cesare

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**Author:** ![Cesare.Garlati](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/cesare.garlati/32/465_2.png) [@Cesare.Garlati](https://forums.sifive.com/u/Cesare.Garlati)\
**Post date:** [May 30, 2018, 12:51am UTC](https://forums.sifive.com/t/sifive-e31-fpga-eval-kit-pmp-in-u-mode/1252/4 "2018-05-30T00:51:58Z")

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After further investigation it appears that PMP access control is enforced only for load & store and not for execution.

Any ideas / suggestions?

Thanks!

Cesare