# RISCV interrupts

**URL:** <https://forums.sifive.com/t/riscv-interrupts/3323>\
**Category:** RISC-V\
**Created:** [February 11, 2020, 9:59am UTC](https://forums.sifive.com/t/riscv-interrupts/3323 "2020-02-11T09:59:20Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![muneeb\_sifive](https://avatars.discourse-cdn.com/v4/letter/m/b5a626/32.png) [@muneeb\_sifive](https://forums.sifive.com/u/muneeb_sifive)\
**Post date:** [February 11, 2020, 9:59am UTC](https://forums.sifive.com/t/riscv-interrupts/3323/1 "2020-02-11T09:59:20Z")

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I want to ask about interrupts dealing in RISV architecture.  
As when any exception or interrupt comes during an execution of program in a pipelined processor, the PC of that unfortunate instruction is stored in SEPC register and after survicing interrupts what PC value is given back either it is PC of that instruction or PC+4 for next instruction in instruction memory.