# RISC-V with vector extension for FPGA

**URL:** <https://forums.sifive.com/t/risc-v-with-vector-extension-for-fpga/3729>\
**Category:** SiFive RISC-V Core IP Evaluation\
**Created:** [June 4, 2020, 12:59pm UTC](https://forums.sifive.com/t/risc-v-with-vector-extension-for-fpga/3729 "2020-06-04T12:59:48Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![sgadol](https://avatars.discourse-cdn.com/v4/letter/s/e480ec/32.png) [@sgadol](https://forums.sifive.com/u/sgadol)\
**Post date:** [June 4, 2020, 12:59pm UTC](https://forums.sifive.com/t/risc-v-with-vector-extension-for-fpga/3729/1 "2020-06-04T12:59:48Z")

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Hi,

I would like to know if there is any information on RISC-V "V’ extension for FPGA? what is the maximum frequency and if this is working?

Thanks  
Shlomi

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**Author:** ![jimw](https://avatars.discourse-cdn.com/v4/letter/j/f14d63/32.png) [@jimw](https://forums.sifive.com/u/jimw)\
**Post date:** [June 5, 2020, 6:15pm UTC](https://forums.sifive.com/t/risc-v-with-vector-extension-for-fpga/3729/2 "2020-06-05T18:15:04Z")

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The V extension is still in draft form, and still changing in ways that cause major incompatibilities, so there is no useful V extension support anywhere at present. I’m not aware of any free cores with draft V extension support at this time. Given the amount of effort, and the fact that things are still changing rapidly, it could be a while before there are any free implementations. There are multiple companies including SiFive working on V extension implementations, that are changing as the V extension changes. You would have to contact sales if interested in getting access to that from SiFive.