RISC-V: why Super Scalar, not VLIW?

More HW complexity for Super Scalar and better SW compatibility.
But more one bit in ISA and less HW complexity for VLIW .
Why choose Super Scalar not VLIW in the beginning ?

RISC-V is designed to be a general-purpose ISA.

Slide 38 summarizes why VLIW has failed in general-purpose computing http://inst.eecs.berkeley.edu/~cs152/sp18/lectures/L13-VLIW.pdf

Do not believe anyone who says they have a great statically scheduled machine.
Only trust measured compiled results with real world complex code (not just vector loops) on real hardware.

Dynamically scheduled In-order superscalars are about the same complexity as statically scheduled VLIW processors that support binary-code compatibility and code compression.

Many thanks, Krste. I see your point and list the slide here for others:

Limits of StaBc Scheduling
§ Unpredictable branches
§ Variable memory latency (unpredictable cache misses)
§ Code size explosion
§ Compiler complexity
§ Despite several attempts, VLIW has failed in general-purpose computer arena (so far).
– More complex VLIW architectures are close to in-order superscalar in complexity, no real advantage on large complex apps.
§ Successful in embedded DSP market
– Simpler VLIWs with more constrained environment, friendlier code.