# \[RISC-V Full System Simulator\] MARSS-RISCV: Micro-ARchitectural Full System Simulator for RISC-V

**URL:** <https://forums.sifive.com/t/risc-v-full-system-simulator-marss-riscv-micro-architectural-full-system-simulator-for-risc-v/2789>\
**Category:** RISC-V\
**Created:** [August 23, 2019, 3:38pm UTC](https://forums.sifive.com/t/risc-v-full-system-simulator-marss-riscv-micro-architectural-full-system-simulator-for-risc-v/2789 "2019-08-23T15:38:27Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![gkothar1](https://avatars.discourse-cdn.com/v4/letter/g/2bfe46/32.png) [@gkothar1](https://forums.sifive.com/u/gkothar1)\
**Post date:** [August 23, 2019, 3:38pm UTC](https://forums.sifive.com/t/risc-v-full-system-simulator-marss-riscv-micro-architectural-full-system-simulator-for-risc-v/2789/1 "2019-08-23T15:38:27Z")

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Hi,

The CAPS Research Group at SUNY-Binghamton (Binghamton University) announces the availability of **MARSS-RISCV: Micro-ARchitectural System Simulator for RISC-V** , a true full system, cycle-accurate simulator for RISC-V processors built upon [TinyEMU](https://bellard.org/tinyemu/) by Fabrice Bellard and uses its code for all the device emulation and configuration. MARSS-RISCV can simulate the execution of applications, OS (including system calls), libraries, interrupt handlers and boot loaders, cycle-by-cycle on pipelined implementations.  
Some of the features of MARSS-RISCV include:

- True full system simulation: simulates in a cycle-accurate fashion the execution of instructions in the entire software stack including the boot-loader, system calls and OS code, libraries, interrupt handlers, user level applications etc.
- Fully configurable, cycle-accurate, in-order and out-of-order single-core RISC-V CPU with support for:
  - RV32GC and RV64GC (user level ISA version 2.2, privileged architecture version 1.10)
  - Multiple execution units with configurable latencies (execution units can be configured to be pipelined)
  - 2-level cache hierarchy with various allocation and miss handling policies
  - A simple DRAM model that accounts for open-page hits
  - A variety of branch predictors: bi-modal and 2-level adaptive (Gshare, Gselect, GAg, GAp, PAg, PAp)

- Supports VirtIO console, network, block device, input and 9P filesystem.
- MARRS-RISCV is easy to install, use and modify and uses a JSON configuration file

The simulator is currently in alpha status as we are validating the cycle accuracy using various development boards. The development of MARRS-RISCV is supported in part by the DARPA SSITH program.

For more information, please visit: [https://github.com/bucaps/marss-riscv](https://github.com/bucaps/marss-riscv)

We look forward to the valuable feedback from the RISC-V community and potential users.

Regards & Thanks,  
CAPS Team