# Relocation truncated to fit: R\_RISCV\_HI20 **URL:** \ **Category:** Freedom U500\ **Created:** [June 2, 2019, 1:30pm UTC](https://forums.sifive.com/t/relocation-truncated-to-fit-r-riscv-hi20/2430 "2019-06-02T13:30:26Z")\ **Posts on this page:** 5\ **Page:** 1
**Author:** ![thomascp](https://avatars.discourse-cdn.com/v4/letter/t/ecc23a/32.png) [@thomascp](https://forums.sifive.com/u/thomascp)\ **Post date:** [June 2, 2019, 1:30pm UTC](https://forums.sifive.com/t/relocation-truncated-to-fit-r-riscv-hi20/2430/1 "2019-06-02T13:30:26Z")
Hi, When I build an image, I met this problem “relocation truncated to fit: R\_RISCV\_HI20”. As far as I know, this is caused when the relocated symbols referenced by the functions are far away and beyond 0x7FFFFFFF. But I check the link script, it seems to be close enough and map file also gives the evidence. This is part of the map file: .text.blink1 0x000000008000034a 0x38 …/app/libapp.a(main.c.obj) 0x000000008000034a blink1 .bss.\_kernel 0x0000000080004398 0x70 kernel/libkernel.a(sched.c.obj) 0x0000000080004398 \_kernel And link script is here, and please notice CONFIG\_XIP is not defined. [link script](https://raw.githubusercontent.com/zephyrproject-rtos/zephyr/v1.14-branch/include/arch/riscv32/common/linker.ld) BR, Peng ---
**Author:** ![jimw](https://avatars.discourse-cdn.com/v4/letter/j/f14d63/32.png) [@jimw](https://forums.sifive.com/u/jimw)\ **Post date:** [June 2, 2019, 3:34pm UTC](https://forums.sifive.com/t/relocation-truncated-to-fit-r-riscv-hi20/2430/2 "2019-06-02T15:34:59Z")
The default code model, medlow, can only access addresses below 0x80000000 on a 64-bit part, or the entire memory on a 32-bit part due to wraparound. If you want to access memory above 2GB on a 64-bit part, you have to use the medany code model, via the -mcmodel=medany compiler option. If you are linking with libraries, like the C library, then those libraries must also be compiled with medany. It you are building your own toolchain, this works best if you use --with-cmodel=medany when configuring. The toolchains on the SiFive web site are configured this way. ---
**Author:** ![thomascp](https://avatars.discourse-cdn.com/v4/letter/t/ecc23a/32.png) [@thomascp](https://forums.sifive.com/u/thomascp)\ **Post date:** [June 3, 2019, 7:53am UTC](https://forums.sifive.com/t/relocation-truncated-to-fit-r-riscv-hi20/2430/3 "2019-06-03T07:53:50Z")
This is helpful! Thanks Jim. And is there any more introduction about code model? I would like to study it. ---
**Author:** ![jimw](https://avatars.discourse-cdn.com/v4/letter/j/f14d63/32.png) [@jimw](https://forums.sifive.com/u/jimw)\ **Post date:** [June 3, 2019, 4:29pm UTC](https://forums.sifive.com/t/relocation-truncated-to-fit-r-riscv-hi20/2430/4 "2019-06-03T16:29:13Z")
Palmer did a blog series about the toolchain. Part four talks about code models. > **[All Aboard, Part 4: The RISC-V Code Models - SiFive](https://www.sifive.com/blog/all-aboard-part-4-risc-v-code-models)** > > The RISC-V ISA was designed to be both simple and modular. In order to > achieve these design goals, RISC-V minimizes one of the largest costs in > implementing complex ISAs: addressing modes. Addressing modes are > expensive both in small designs (due to... You might be interested in reading the entire series from the beginning > **[All Aboard, Part 0: Introduction - SiFive](https://www.sifive.com/blog/all-aboard-part-0-introduction)** > > I'm Palmer Dabbelt, a software engineer at SiFive and a maintainer of > various RISC-V ports. I've been working with the RISC-V ISA for a few > years, and it's finally starting to get ready for prime-time. We're not > yet upstream in Linux or glibc, but... ---
**Author:** ![thomascp](https://avatars.discourse-cdn.com/v4/letter/t/ecc23a/32.png) [@thomascp](https://forums.sifive.com/u/thomascp)\ **Post date:** [June 4, 2019, 10:15am UTC](https://forums.sifive.com/t/relocation-truncated-to-fit-r-riscv-hi20/2430/5 "2019-06-04T10:15:51Z")
Yeah, thank you!