# Program sdk executable in FPGA RAM

**URL:** <https://forums.sifive.com/t/program-sdk-executable-in-fpga-ram/2844>\
**Category:** SiFive RISC-V Core IP Evaluation\
**Created:** [September 13, 2019, 10:36am UTC](https://forums.sifive.com/t/program-sdk-executable-in-fpga-ram/2844 "2019-09-13T10:36:50Z")\
**Posts on this page:** 1\
**Page:** 1

<div class="post-metadata">

**Author:** ![grs1b](https://avatars.discourse-cdn.com/v4/letter/g/77aa72/32.png) [@grs1b](https://forums.sifive.com/u/grs1b)\
**Post date:** [September 13, 2019, 10:36am UTC](https://forums.sifive.com/t/program-sdk-executable-in-fpga-ram/2844/1 "2019-09-13T10:36:50Z")

</div>

I believe only Olimex and J-Link are supported JTAG present for sdk. At this stage i don’t have either of them but i am planning to order one.

Is there a way i can program sdk executable as a part of bitstream. Xilinx having support to generate bitstream with elf(procedure given in following link) . but does anyone tried it for sifive IP core.

> **[AR# 63041: Vivado IP Integrator - How to populate the BRAM in processorless IP...](https://www.xilinx.com/support/answers/63041.html)**
>
> Processor-less block RAM (BRAM) systems are a popular use-case in FPGA solutions. However, currently the Vivado tool will not allow the user to associate ELF to processor-less Block Memory Generators (BMG). This answer record contains work-arounds...

this feature also useful for production fpga bitstream.  
Does sifive have any plan to support any other jtag vendor?