# Problem synthesizing Verilog created by Chisel

**URL:** <https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333>\
**Category:** Freedom E300\
**Created:** [February 12, 2017, 9:00pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333 "2017-02-12T21:00:25Z")\
**Posts on this page:** 1\
**Showing post:** 21

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**Author:** ![dagema](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dagema/32/59_2.png) [@dagema](https://forums.sifive.com/u/dagema)\
**Post date:** [February 15, 2017, 3:55pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/21 "2017-02-15T15:55:10Z")

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Hi Megan,

I get errors when running any of the tcl scripts. Can it be that I am in the “wasn`t meant for Windows” trap?

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