# Problem synthesizing Verilog created by Chisel

**URL:** <https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333>\
**Category:** Freedom E300\
**Created:** [February 12, 2017, 9:00pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333 "2017-02-12T21:00:25Z")\
**Posts on this page:** 14\
**Page:** 2

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**Author:** ![dagema](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dagema/32/59_2.png) [@dagema](https://forums.sifive.com/u/dagema)\
**Post date:** [February 15, 2017, 3:55pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/21 "2017-02-15T15:55:10Z")

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Hi Megan,

I get errors when running any of the tcl scripts. Can it be that I am in the “wasn`t meant for Windows” trap?

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**Author:** ![dagema](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dagema/32/59_2.png) [@dagema](https://forums.sifive.com/u/dagema)\
**Post date:** [February 15, 2017, 7:23pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/22 "2017-02-15T19:23:32Z")

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> [@mwachs5](#):
>
> I also see that it is not finding the generated IP. You will need to generate the IP so you can use it (this is for the clock generation block and the System Reset block. In the freedom flow, this is done by a TCL script:

I set the system.v file to top, and worked out the right sequence for running the tcl scripts to get the ip generated, but I am still getting the “set\_property” errors in the XDC contraint files:

 ![](https://us1.discourse-cdn.com/flex020/uploads/sifive/original/1X/e9353f59f85d0a092bf3f1cc8a6403bc157d3abd.png)

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**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\
**Post date:** [February 15, 2017, 7:28pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/23 "2017-02-15T19:28:40Z")

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What is on the line it’s complaining about?

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<div class="post-metadata">

**Author:** ![dagema](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dagema/32/59_2.png) [@dagema](https://forums.sifive.com/u/dagema)\
**Post date:** [February 15, 2017, 8:33pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/24 "2017-02-15T20:33:03Z")

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> [@mwachs5](#):
>
> W

Well, this is embarrassing, but after I restarted Vivado the synthesis and impeimentation ran without errors. 😊

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**Author:** ![dagema](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dagema/32/59_2.png) [@dagema](https://forums.sifive.com/u/dagema)\
**Post date:** [February 17, 2017, 5:14pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/25 "2017-02-17T17:14:58Z")

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Hi Megan,

I am trying to get around the cricial warnings issued on three lines of the arty-master.xdc constraint file. The error message is saying that the objects clkbfout\_mmcm\_1, clk\_out1\_mmcm\_1 and clk\_out2\_mmcm\_1 do not exist in the design, but when I run “report\_clocks” they do appear. And since the xdc file is the last to be compiled, I don’t think it can be caused by wrong compile sequence. Do you have any hints? Is it OK to just ignore these warnings?

 ![](https://us1.discourse-cdn.com/flex020/uploads/sifive/original/1X/ca701efdc1e4097d310d67f4277dfdb07323c06c.png)

 ![](https://us1.discourse-cdn.com/flex020/uploads/sifive/original/1X/a0a45a3ff57d08d741a5242e840af322d8a507a9.png)

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**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\
**Post date:** [March 10, 2017, 3:35pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/26 "2017-03-10T15:35:39Z")

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Hi Donnie,

Were you able to get your design compiling successfully even with those warnings? I will take a look at our flow and see if the warnings exist and perhaps we should just remove those lines from the constraint file. I’m guessing those constraints don’t apply anymore to this design.

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**Author:** ![dagema](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dagema/32/59_2.png) [@dagema](https://forums.sifive.com/u/dagema)\
**Post date:** [March 10, 2017, 4:52pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/27 "2017-03-10T16:52:13Z")

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Well, I can generate a bitfile, but the implementation is failing so many timing restrictions that a am rather hesitant to upload it to the Arty.

 ![](https://us1.discourse-cdn.com/flex020/uploads/sifive/original/1X/e886d4c2ca794ed7045b9b97ab145a6578361784.png)

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**Author:** ![mwachs5](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mwachs5/32/13_2.png) [@mwachs5](https://forums.sifive.com/u/mwachs5)\
**Post date:** [March 10, 2017, 9:51pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/28 "2017-03-10T21:51:52Z")

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Hm, where did you get that constraint file arty-master.xdc from? It looks different from the one here:

[https://github.com/sifive/freedom/blob/master/fpga/e300artydevkit/constrs/arty-master.xdc#L9](https://github.com/sifive/freedom/blob/master/fpga/e300artydevkit/constrs/arty-master.xdc#L9)

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<div class="post-metadata">

**Author:** ![dagema](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dagema/32/59_2.png) [@dagema](https://forums.sifive.com/u/dagema)\
**Post date:** [March 10, 2017, 11:05pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/29 "2017-03-10T23:05:49Z")

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I got the constraint file here: freedom/fpga/e300artydefkit/constrs/arty-master.xdc  
The contrent is identical, at least as far as what you posted.

## This file is a general .xdc for the ARTY Rev. B

## To use it in a project:

## - uncomment the lines corresponding to used pins

## - rename the used ports (in each line, after get\_ports) according to the top level signal names in the project

## Clock signal

set\_property -dict { PACKAGE\_PIN E3 IOSTANDARD LVCMOS33 } [get\_ports { CLK100MHZ }]; #IO\_L12P\_T1\_MRCC\_35 Sch=gclk[100]  
create\_clock -add -name sys\_clk\_pin -period 10.00 -waveform {0 5} [get\_ports {CLK100MHZ}];

##Switches

set\_property -dict { PACKAGE\_PIN A8 IOSTANDARD LVCMOS33 } [get\_ports { sw\_0 }]; #IO\_L12N\_T1\_MRCC\_16 Sch=sw[0]  
set\_property -dict { PACKAGE\_PIN C11 IOSTANDARD LVCMOS33 } [get\_ports { sw\_1 }]; #IO\_L13P\_T2\_MRCC\_16 Sch=sw[1]  
set\_property -dict { PACKAGE\_PIN C10 IOSTANDARD LVCMOS33 } [get\_ports { sw\_2 }]; #IO\_L13N\_T2\_MRCC\_16 Sch=sw[2]  
set\_property -dict { PACKAGE\_PIN A10 IOSTANDARD LVCMOS33 } [get\_ports { sw\_3 }]; #IO\_L14P\_T2\_SRCC\_16 Sch=sw[3]

##RGB LEDs

set\_property -dict { PACKAGE\_PIN E1 IOSTANDARD LVCMOS33 } [get\_ports { led0\_b }]; #IO\_L18N\_T2\_35 Sch=led0\_b  
set\_property -dict { PACKAGE\_PIN F6 IOSTANDARD LVCMOS33 } [get\_ports { led0\_g }]; #IO\_L19N\_T3\_VREF\_35 Sch=led0\_g  
set\_property -dict { PACKAGE\_PIN G6 IOSTANDARD LVCMOS33 } [get\_ports { led0\_r }]; #IO\_L19P\_T3\_35 Sch=led0\_r  
set\_property -dict { PACKAGE\_PIN G4 IOSTANDARD LVCMOS33 } [get\_ports { led1\_b }]; #IO\_L20P\_T3\_35 Sch=led1\_b  
set\_property -dict { PACKAGE\_PIN J4 IOSTANDARD LVCMOS33 } [get\_ports { led1\_g }]; #IO\_L21P\_T3\_DQS\_35 Sch=led1\_g  
set\_property -dict { PACKAGE\_PIN G3 IOSTANDARD LVCMOS33 } [get\_ports { led1\_r }]; #IO\_L20N\_T3\_35 Sch=led1\_r  
set\_property -dict { PACKAGE\_PIN H4 IOSTANDARD LVCMOS33 } [get\_ports { led2\_b }]; #IO\_L21N\_T3\_DQS\_35 Sch=led2\_b  
set\_property -dict { PACKAGE\_PIN J2 IOSTANDARD LVCMOS33 } [get\_ports { led2\_g }]; #IO\_L22N\_T3\_35 Sch=led2\_g  
set\_property -dict { PACKAGE\_PIN J3 IOSTANDARD LVCMOS33 } [get\_ports { led2\_r }]; #IO\_L22P\_T3\_35 Sch=led2\_r

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<div class="post-metadata">

**Author:** ![dagema](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dagema/32/59_2.png) [@dagema](https://forums.sifive.com/u/dagema)\
**Post date:** [March 11, 2017, 12:39pm UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/30 "2017-03-11T12:39:38Z")

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> [@mwachs5](#):
>
> Hm, where did you get that constraint file arty-master.xdc from? It looks different from the one here:

I assume you are referring to the lines following 231. I checked my pulled github directory and find also only 231 lines. The file is actually the same as you referenced. Vivado must have added those new lines automatically. I deleted them and reran the implementation. The 4 related critical errors dissappeared, but the timing errors still remain.

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**Author:** ![dagema](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dagema/32/59_2.png) [@dagema](https://forums.sifive.com/u/dagema)\
**Post date:** [March 24, 2017, 9:13am UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/31 "2017-03-24T09:13:26Z")

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. . . getting some moral support - always welcome! 😍

 ![](https://us1.discourse-cdn.com/flex020/uploads/sifive/original/1X/3ece887daee96b8404719b5bc559a8f990483714.jpg)  
 ![](https://us1.discourse-cdn.com/flex020/uploads/sifive/original/1X/56bdedffa79a0e3f484333ea3ca291ba062da172.jpg)

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<div class="post-metadata">

**Author:** ![dagema](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/dagema/32/59_2.png) [@dagema](https://forums.sifive.com/u/dagema)\
**Post date:** [May 18, 2018, 8:45am UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/32 "2018-05-18T08:45:05Z")

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Hi Bruce,

> [@brucehoult](#):
>
> What’s the utilisation like on LUTs/slices etc? Curious how much space is spare. Could two cores be implemented in the Arty?

For what it`s worth, I just ran across a post spelling out some [advantages of using LiteX for FPGA developement](https://www.bunniestudios.com/blog/?p=5018), which suggests a four-fold reduction in fabric utilization and faster synthesis. I have not tried it out yet, but I do intend to do so, as it might enable getting multiple HiFive1 cores into the Arty and/or Z7.

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**Author:** ![bruce](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/bruce/32/452_2.png) [@bruce](https://forums.sifive.com/u/bruce)\
**Post date:** [May 18, 2018, 9:03am UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/33 "2018-05-18T09:03:14Z")

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Cool. Hopefully I’ll be able to start seriously playing with FPGAs soon, now this stuff is not just for unused evenings.

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**Author:** ![bruce](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/bruce/32/452_2.png) [@bruce](https://forums.sifive.com/u/bruce)\
**Post date:** [May 18, 2018, 9:11am UTC](https://forums.sifive.com/t/problem-synthesizing-verilog-created-by-chisel/333/34 "2018-05-18T09:11:19Z")

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Reading Bunnie’s article, it seems that LiteX is something comparable to the Berkeley “Chisel” design language that is used to generate the Verilog for Rocket-based RISC-V cores.

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