Going through the E310G-v1.0 sections 1.5, 1.6, and 2.1, I don’t see the actual pin definitions for the JTAG interface. Presumably there will be a breakout board on the HiFive1, but will the pins be specified as well in upcoming documentation?

Also, what JTAG adapters have been tested with the SiFive fork of openocd? Should I be able to use a standard jlink adapter? What adapter did the team test with?

Thank you,


The HiFive1 board does not have a JTAG header. The USB port connects to a FT2232H chip which does the translation to JTAG, so no external debugger hardware is needed.

For the SiFive fork of OpenOCD, we test our flows with the Olimex ARM-USB-TINY-H, but we just break out the pins as needed for the development kit. We also used the FT2232H Minimodule during our prototyping.

We have not tried using the JLink debuggers.

You may want to refer to the E310 Getting Started guide for more information about the debugger interface:



Also, I realized I didn’t answer your actual question. Yes, we will provide the pinout for the QFN48-pin package in our next release of the docs (this week).


Hi Megan,

Nice! Thanks. I should’ve figured you used the Olimex as it’s on the devkit web page. And thanks for pointing me to the Arty document as I didn’t realize some of the details would be common to the HiFive1 board, but that makes sense.

The Arty doc doesn’t provide an actual openocd command line example and points to the SDK. This is fine, but for my Harvest OS toolchain I like to inline the openocd call. Presumably the interface is ‘interface/ftdi/minimodule.cfg’ but what is the target? I can’t find a RISC-V or fe310g target in the SiFive openocd fork.

Thank you,

Ah, the target is ‘riscv’ :

The actual interface files that we use can be found in the Freedom E Dev Kit:


We’ve also written an OpenOCD Flash driver, fespi, which drives the Freedom E310 QSPI Flash interface. We use it to load code to the SPI Flash connected to the FE310 (both the HiFive1 and FE310 Arty Dev Kit use similar Flash interface).

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Excellent. Thanks for the details, Megan. Can’t wait for the board to come in :slight_smile:


Megan, can you drop any other hints about what the next round of documentation contains?

How do you debug the board for using JTAG?

You cannot use JTAG directly on the HiFive1. But you can use USB to access the JTAG interface on the chip.

Suggest that you read the Freedom Studio manual (for using Freedom Studio):

Or if you want to use the Freedom E SDK directly, refer to the Getting Started Guide (for using Freedom E SDK):

I have a detailed question about one of the OpenOCD commands in the “sifive-freedom-e300-hifive1.cfg”…

The ftdi_layout_init command includes 0x0008 and 0x001b as parameters. I don’t get how this configures the FT2232HL part to place port A into MPSSE mode. The OpenOCD documentation says that “ftdi_layout_init command”:

“Specifies the initial values of the FTDI GPIO data and direction registers. Each value is a 16-bit number corresponding to the concatenation of the high and low FTDI GPIO registers. The values should be selected based on the schematics of the adapter, such that all signals are set to safe levels with minimal impact on the target system. Avoid floating inputs, conflicting outputs and initially asserted reset signals.”

When I look through the FT2232H documentation and FTDI Application Notes, there is no mention of “data” or “direction” registers. Also the hifive-a01-schematics aren’t wired up to use the ADBUS4 or BDBUS3 port bits which would seem like what the extra bits in 0x001b and 0x0008 respectively would be used for.

I’m pretty certain I’m not looking in the right documentation to understand this.

Could someone with more domain knowledge please just point me in the right direction so I don’t waste a lot more time on this?

Thanks in advance.