Maximum serial clock frequency on HiFive1?

HiFive1 Rev B
1

What’s the maximum serial clock frequency on HiFive1 for the QSPI flash? The chip gives 3 potential options depending on the usage mode but I’m unclear on which mode is being used by the memory mapped flash.

1 Like
2

After reset, the SPI flash controller is pre-configured to use the “normal read” command 0x3 in purely serial mode. By default, no dummy cycles are inserted, which limits the IS25LP128 flash device to a maximum frequency of 50 MHz. This can be increased to 133 MHz by using the “fast read” command 0xb with 8 dummy cycles, according to Table 6.9 on page 16 of the datasheet.

3

Thanks, I realized I didn’t ask the question I meant to but your answer implied it was possible to change the values and led me to the answer to the question I didn’t ask. The memory mapped flash SPI interface is configured via the ffmt register. Somehow I had glossed over that when reading the manuals.

4

This is how I’m trying to setup the XIP to use “fast read” but it does not work. Note this is a HiFive1. A few instructions afterwards I get an illegal instruction that I assume is due to an improperly filled I-cache miss. Is there something obviously wrong?

The code does work fine if I set SPI_REG_SCKDIV=2 or with cpuclk @ 200MHz and SCKDIV=1. Unfortunately I’m not able to look at the signals.

What is the proper way to setup the XIP flash for higher speeds and to use dual SPI mode?

	SPI0_REG(SPI_REG_SCKDIV) = SCKDIV_SAFE;

	PRCI_set_hfrosctrim_for_f_cpu(266000000, PRCI_FREQ_UNDERSHOOT);

	SPI0_REG(SPI_REG_FFMT) =
	   SPI_INSN_CMD_EN         | // Enable memory-mapped flash
	   SPI_INSN_ADDR_LEN(3)    | // 25LP128 read commands have 3 address bytes
	   SPI_INSN_PAD_CNT(8)     | // See 25LP128 Table 6.9 Read Dummy Cycles
	   SPI_INSN_CMD_PROTO(SPI_PROTO_S) | // 25LP128 Table 8.1 "Instruction
	   SPI_INSN_ADDR_PROTO(SPI_PROTO_S)| //  Set" shows mode for cmd, addr, and
	   SPI_INSN_DATA_PROTO(SPI_PROTO_S)| //  data protocol for given instruction
	   SPI_INSN_CMD_CODE(0x0b) | // Set the instruction to "Fast Read Dual I/O"
	   SPI_INSN_PAD_CODE(0x00);  // Dummy cycle sends 0 value bits

	SPI0_REG(SPI_REG_SCKDIV) = 0; // set SCK to 133Mhz
}
5

There is certainly a physical limit on the speed of the pins and the lines on the PCB. SCK at 133 MHz is very likely above that limit. You’d best keep it < 100 MHz, and “safe” operation would be 40MHz.