# Master thesis related to RISC-V

**URL:** <https://forums.sifive.com/t/master-thesis-related-to-risc-v/1842>\
**Category:** General\
**Created:** [December 7, 2018, 6:29pm UTC](https://forums.sifive.com/t/master-thesis-related-to-risc-v/1842 "2018-12-07T18:29:12Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![mart256](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/mart256/32/968_2.png) [@mart256](https://forums.sifive.com/u/mart256)\
**Post date:** [December 7, 2018, 6:29pm UTC](https://forums.sifive.com/t/master-thesis-related-to-risc-v/1842/1 "2018-12-07T18:29:12Z")

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Hello everyone, my name is Martin and I’m currently studying Ms. in Computer Science. Next year (2019) I have to start working on my master thesis, which is a work of 1 year long. My area of interest is Computer Organization (Architecture), and my secondary area of interest is Operating Systems, I’m very fond of hardware. (My bachelor degree is Electrical Engineering).

I am excited about this open source ISA called RISC-V. I wonder on what topic could I work for an entire one year thesis related to RISC-V? I’d like a topic where I’d have to get my hands dirty, for example, working with a RISC-V core on a FPGA with verilog and tuning the OS, for example.

I’m very opened to ideas or suggestions, which are highly appreciated.

Regards.

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**Author:** ![Atif](https://avatars.discourse-cdn.com/v4/letter/a/9de053/32.png) [@Atif](https://forums.sifive.com/u/Atif)\
**Post date:** [April 19, 2019, 6:00pm UTC](https://forums.sifive.com/t/master-thesis-related-to-risc-v/1842/2 "2019-04-19T18:00:48Z")

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Martin:

Please check out our new FireFly board ([www.pixilica.com](http://www.pixilica.com)). It is intended exactly for the kinds of applications you envision in an academic environment. We can send you a board to try out.

Best  
Atif Zafar.  
CEO  
Pixilica, LLC  
[Atif@Pixilica.com](mailto:Atif@Pixilica.com)