Machine-readable register description files for SiFive chips


#1

In Rust Embedded Working Group we use SVD files for different MCUs to generate Rust peripheral access bindings with svd2rust tool. These files are normally provided by vendor. However, for SiFive chips we do not have anything like this so far and the only SVD for FE310-G000 chip was created by hand. This approach is time-consuming and error-prone.

In our RISC-V team we are trying to provide Rust support for different chips available on the market. We also have plans for supporting FU540. This chip is much more complicated compared to FE310, so it will be incredibly helpful if you provide register descriptions for it. For FE310 chips it would also be useful to have register descriptions provided by vendor to check that our hand-written version does not have bugs. Having an SVD description is not mandatory, I hope that any other machine-readable format will also work for us.

Additionally, some people use SVD files with gdb to improve debugging experience.


(Wladimir van der Laan) #3

yes please !


#4

I was looking around for what’s the status of SVD like system in RISCV, for code generation templating. I think the concern is that SVD is an ARM technology and there may be legal issue in using it.

However I also saw that there is XSVD which is a rework of the Arm CMSIS SVD, but cleaned, extended and rewritten in JSON instead of XML.

https://xpack.github.io/xsvd/files/xsvd-json/

You may want to look into this project instead and see if SiFive would be more interested in this tech instead.