# Ld, sd alignment?

**URL:** <https://forums.sifive.com/t/ld-sd-alignment/5530>\
**Category:** HiFive Unmatched\
**Created:** [December 27, 2021, 2:11pm UTC](https://forums.sifive.com/t/ld-sd-alignment/5530 "2021-12-27T14:11:57Z")\
**Posts on this page:** 1\
**Showing post:** 6

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**Author:** ![pa4wdh](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pa4wdh](https://forums.sifive.com/u/pa4wdh)\
**Post date:** [December 29, 2021, 9:44pm UTC](https://forums.sifive.com/t/ld-sd-alignment/5530/6 "2021-12-29T21:44:32Z")

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I was trying to make sense of this huge impact of unaligned memory access, and with Jessica’s hint that OpenSBI handles this i found the actual code that handles this: [opensbi/sbi\_misaligned\_ldst.c at master · riscv-software-src/opensbi · GitHub](https://github.com/riscv-software-src/opensbi/blob/master/lib/sbi/sbi_misaligned_ldst.c)

I’m trying to figure out what happens to see if i can explain the huge impact:

1. The program tries to do an unaligned read/write
2. This event gets noticed and trapped by the CPU, switches to M-mode
3. The OpenSBI trap handler gets called ([opensbi/sbi\_trap.c at master · riscv-software-src/opensbi · GitHub](https://github.com/riscv-software-src/opensbi/blob/master/lib/sbi/sbi_trap.c))
4. The trap handler determines the trap is because of misalignment, and calls the appropriate function
5. This function “emulates” the misaligned access using aligned reads/writes and shifts
6. CPU switches back to U-mode and program execution resumes

Is there anything i’ve missed?

I guess this already explains a lot 🙂

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