# Ld, sd alignment? **URL:** \ **Category:** HiFive Unmatched\ **Created:** [December 27, 2021, 2:11pm UTC](https://forums.sifive.com/t/ld-sd-alignment/5530 "2021-12-27T14:11:57Z")\ **Posts on this page:** 7\ **Page:** 1
**Author:** ![abirtz](https://avatars.discourse-cdn.com/v4/letter/a/71e660/32.png) [@abirtz](https://forums.sifive.com/u/abirtz)\ **Post date:** [December 27, 2021, 2:11pm UTC](https://forums.sifive.com/t/ld-sd-alignment/5530/1 "2021-12-27T14:11:57Z")
What is the requirement for the instruction "ld t0,a(0) by example ? 8 bytes, 4 bytes or no alignment for a0 ? ---
**Author:** ![JimWilson](https://avatars.discourse-cdn.com/v4/letter/j/3be4f8/32.png) [@JimWilson](https://forums.sifive.com/u/JimWilson)\ **Post date:** [December 27, 2021, 5:08pm UTC](https://forums.sifive.com/t/ld-sd-alignment/5530/2 "2021-12-27T17:08:30Z")
8 bytes. SiFive cores require natural alignment for all loads and stores. There is no misaligned/unaligned support, unless you write a trap handler to emulate it. ---
**Author:** ![pa4wdh](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pa4wdh](https://forums.sifive.com/u/pa4wdh)\ **Post date:** [December 28, 2021, 8:55am UTC](https://forums.sifive.com/t/ld-sd-alignment/5530/3 "2021-12-28T08:55:40Z")
Some time ago i got curious about the impact of unaligned memory access and wrote a little asm program to do 0xfffffff reads/writes with ld, lw, lh, lb, sd, sw, sh and sb with different offsets and timed it with the “time” utility. These are the results, all times are in seconds: (The forum doesn’t support tables so i’ll use code tags 🙂 ) ```auto ld lw lh lb sd sw sh sb offset time time time time time time time time 0 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 1 158.87 111.66 90.05 0.45 152.76 106.36 85.14 0.45 2 158.76 111.64 0.45 0.45 153.57 106.35 0.45 0.45 3 158.83 111.64 90.05 0.45 151.80 106.39 85.15 0.45 4 159.04 0.45 0.45 0.45 151.79 0.45 0.45 0.45 5 158.85 111.66 90.02 0.45 151.81 106.35 85.15 0.45 6 158.43 111.64 0.45 0.45 153.34 106.34 0.45 0.45 7 158.90 111.65 90.07 0.45 151.80 106.37 85.14 0.45 8 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 ``` As you can see the impact is huge when it’s not aligned at the size of the read/write. ---
**Author:** ![abirtz](https://avatars.discourse-cdn.com/v4/letter/a/71e660/32.png) [@abirtz](https://forums.sifive.com/u/abirtz)\ **Post date:** [December 28, 2021, 9:04pm UTC](https://forums.sifive.com/t/ld-sd-alignment/5530/4 "2021-12-28T21:04:06Z")
Whoo! unaligned time grow by factor 350… Thank you to share your result. ---
**Author:** ![jrtc27](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/jrtc27/32/1352_2.png) [@jrtc27](https://forums.sifive.com/u/jrtc27)\ **Post date:** [December 29, 2021, 9:23pm UTC](https://forums.sifive.com/t/ld-sd-alignment/5530/5 "2021-12-29T21:23:00Z")
Yes, when you have no hardware support, M-mode firmware like OpenSBI will handle the alignment faults and emulate the accesses, so it’s always going to be orders of magnitude slower than having unaligned accesses supported in the hardware itself. Although they’re required to _work_ in S-mode and above, you should just avoid them, especially in C where it’s undefined behaviour; use memcpy/memset and let the compiler inline an unaligned access if it decides that’s the best way to implement it. ---
**Author:** ![pa4wdh](https://avatars.discourse-cdn.com/v4/letter/p/a88e57/32.png) [@pa4wdh](https://forums.sifive.com/u/pa4wdh)\ **Post date:** [December 29, 2021, 9:44pm UTC](https://forums.sifive.com/t/ld-sd-alignment/5530/6 "2021-12-29T21:44:32Z")
I was trying to make sense of this huge impact of unaligned memory access, and with Jessica’s hint that OpenSBI handles this i found the actual code that handles this: [opensbi/sbi\_misaligned\_ldst.c at master · riscv-software-src/opensbi · GitHub](https://github.com/riscv-software-src/opensbi/blob/master/lib/sbi/sbi_misaligned_ldst.c) I’m trying to figure out what happens to see if i can explain the huge impact: 1. The program tries to do an unaligned read/write 2. This event gets noticed and trapped by the CPU, switches to M-mode 3. The OpenSBI trap handler gets called ([opensbi/sbi\_trap.c at master · riscv-software-src/opensbi · GitHub](https://github.com/riscv-software-src/opensbi/blob/master/lib/sbi/sbi_trap.c)) 4. The trap handler determines the trap is because of misalignment, and calls the appropriate function 5. This function “emulates” the misaligned access using aligned reads/writes and shifts 6. CPU switches back to U-mode and program execution resumes Is there anything i’ve missed? I guess this already explains a lot 🙂 ---
**Author:** ![jrtc27](https://sea2.discourse-cdn.com/flex020/user_avatar/forums.sifive.com/jrtc27/32/1352_2.png) [@jrtc27](https://forums.sifive.com/u/jrtc27)\ **Post date:** [December 30, 2021, 6:51pm UTC](https://forums.sifive.com/t/ld-sd-alignment/5530/7 "2021-12-30T18:51:11Z")
Yes, that’s the idea