I have successfully generated Machine timer and machine software interrupt, but writing software for S-mode I couldn’t find any way to generate a Supervisor timer/software interrupt.
According to RISC-V documentation, to generate an interrupt in Supervisor mode, the appropriate bits needs to be set in interrupt & exception delegation register “mideleg”, which I did, interrupt needs to be enabled in SIE (supervisor interrupt enable register) which I also did. I double checked that the delegation is supported by writing all 1s to “mideleg”. But I couldn’t find any register in U54 manual for generation of Supervisor timer/software interrupt. Writing to MSIP or generates a machine mode software interrupt not supervisor software interrupt. Can supervisor software interrupt be generated in S mode to S mode (delegated) or am I missing something in interrupt generation.
I also saw Uboot code, and observed it relies on Supervisor-binary interface (SBI) provided by openSBI to generate machine mode IPIs by using ecall, even it doesn’t SSI (supervisor software interrupt).