# Interrupt entry and exit in FE310-G002

**URL:** <https://forums.sifive.com/t/interrupt-entry-and-exit-in-fe310-g002/5583>\
**Category:** HiFive1 Rev B\
**Created:** [January 26, 2022, 8:58pm UTC](https://forums.sifive.com/t/interrupt-entry-and-exit-in-fe310-g002/5583 "2022-01-26T20:58:14Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![bsvtgc](https://avatars.discourse-cdn.com/v4/letter/b/ce7236/32.png) [@bsvtgc](https://forums.sifive.com/u/bsvtgc)\
**Post date:** [January 26, 2022, 8:58pm UTC](https://forums.sifive.com/t/interrupt-entry-and-exit-in-fe310-g002/5583/1 "2022-01-26T20:58:14Z")

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FE310-G002 manual on section 8.2.1 Interrupt Entry and Exit says the following.  
The value of mstatus.MIE is copied into mcause.MPIE. But there isn’t any MPIE bit in cause register as per RISC-V privileged spec. Is that supposed to be status.MPIE?

Vincent.

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**Author:** ![RalphF](https://avatars.discourse-cdn.com/v4/letter/r/d26b3c/32.png) [@RalphF](https://forums.sifive.com/u/RalphF)\
**Post date:** [January 27, 2022, 9:43pm UTC](https://forums.sifive.com/t/interrupt-entry-and-exit-in-fe310-g002/5583/2 "2022-01-27T21:43:50Z")

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Hi Vincent,

Yes - you’re correct, that is a typo. It should be `mstatus.MPIE` not `mcause.MPIE` in the first bullet and second-to-last bullet in Section 8.2.1.

We’ll get that fixed for the next release of the Manual.

Thank you for helping us improve the documentation.

Regards,  
Ralph