# Initialize and set up of GPIO pins **URL:** \ **Category:** HiFive1 Rev B\ **Created:** [May 15, 2023, 2:16pm UTC](https://forums.sifive.com/t/initialize-and-set-up-of-gpio-pins/6127 "2023-05-15T14:16:20Z")\ **Posts on this page:** 1\ **Showing post:** 2
**Author:** ![pds](https://avatars.discourse-cdn.com/v4/letter/p/8edcca/32.png) [@pds](https://forums.sifive.com/u/pds)\ **Post date:** [May 20, 2023, 4:10am UTC](https://forums.sifive.com/t/initialize-and-set-up-of-gpio-pins/6127/2 "2023-05-20T04:10:49Z")
Hi @Jonny040 I am not familiar with MultiZone but maybe these few notes can shed some light on your question. The [interrupt handling procedural flow](https://forums.sifive.com/t/what-is-plic-interrupt-source-start-and-end-in-interrupt-source-mapping/5705/9) is a detailed discussion and good diagram here in the _forums_. A very lean yet complete working example is [Demonstrating MTVEC](https://github.com/psherman42/Demonstrating-MTVEC) on my github site. In general there’s only a few simple steps: _Assuming you’ve set up `mtvec` properly, enabled the CSR’s `mstatus.MIE` bit, and enabled the appropriate bit of GPIO\_IE_, a) Read PLIC\_CLAIM to get the `source id` of the interrupt request – the 32 GPIO are id’s 8-39 b) Write PLIC\_CLAIM to complete the request of that source c) Jump to desired code d) Write ‘1’ to appropriate bit of GPIO\_IP to clear the pending interrupt e) Exit with the `mret` instruction You don’t need to clear the `mstatus.MIP` bit, because it is cleared _automatically_ when `mret` happens. The specific method of clearing external interrupts varies depending on the nature of the external peripheral whose interrupt you enable; step (d) above is shown in case of GPIO. See the _procedural flow_ discussion above for clearing, for example, the UART, the SPI, the I2C, or the PWM periperals. --- _[View the full topic](https://forums.sifive.com/t/initialize-and-set-up-of-gpio-pins/6127)._