I have downloaded some interesting Core IP FPGA Eval Kits in https://www.sifive.com/core-designer, but I find that the prebuilt .mcs file is generated for Arty_100T. For example, the name of the .mcs file in sifive_coreip_E34_eval_dev_kit_v1p0\fpga is sifive_coreip_E34_FPGA_Evaluation_Arty_100T_v1p0_rc0.mcs.
Unfortunately, I don’t have a Arty board from Digilent or Avent. I’m using a Genesys2 boad with xc7k325t. But I still want to try out your cores on my FPGA. I find that there are some verilog source files in “verilog/design” and “verilog/memories”, which seem could be used in Vivado or Quartus.
I have already tried out the " Freedom E300 Arty FPGA Dev Kit" from https://github.com/sifive/freedom, but I still want to evaluate more cores. So is it possible for me to use these verilog files to generate a useable bitstream file for my FPGA? Could you write some guides on how to put the FPGA Eval Kits into different FPGA?